1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2022 Scott Long 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Thunderbolt 3 register definitions 29 */ 30 31 /* $FreeBSD$ */ 32 33 #ifndef _NHI_REG_H 34 #define _NHI_REG_H 35 36 /* Some common definitions */ 37 #define TBT_SEC_NONE 0x00 38 #define TBT_SEC_USER 0x01 39 #define TBT_SEC_SECURE 0x02 40 #define TBT_SEC_DP 0x03 41 42 #define GENMASK(h, l) (((~0U) >> (31 - (h))) ^ ((~0U) >> (31 - (l)) >> 1)) 43 44 /* PCI Vendor and Device ID's */ 45 #define VENDOR_INTEL 0x8086 46 #define DEVICE_AR_2C_NHI 0x1575 47 #define DEVICE_AR_DP_B_NHI 0x1577 48 #define DEVICE_AR_DP_C_NHI 0x15d2 49 #define DEVICE_AR_LP_NHI 0x15bf 50 #define DEVICE_ICL_NHI_0 0x8a17 51 #define DEVICE_ICL_NHI_1 0x8a0d 52 53 #define VENDOR_AMD 0x1022 54 #define DEVICE_PINK_SARDINE_0 0x1668 55 #define DEVICE_PINK_SARDINE_1 0x1669 56 57 /* * * MMIO Registers 58 * * Ring buffer registers 59 * 60 * 32 transmit and receive rings are available, with Ring 0 being the most 61 * important one. The ring descriptors are 16 bytes each, and each set of 62 * TX and RX descriptors are packed together. There are only definitions 63 * for the Ring 0 addresses, others can be directly computed. 64 */ 65 #define NHI_TX_RING_ADDR_LO 0x00000 66 #define NHI_TX_RING_ADDR_HI 0x00004 67 #define NHI_TX_RING_PICI 0x00008 68 #define TX_RING_CI_MASK GENMASK(15, 0) 69 #define TX_RING_PI_SHIFT 16 70 #define NHI_TX_RING_SIZE 0x0000c 71 72 #define NHI_RX_RING_ADDR_LO 0x08000 73 #define NHI_RX_RING_ADDR_HI 0x08004 74 #define NHI_RX_RING_PICI 0x08008 75 #define RX_RING_CI_MASK GENMASK(15, 0) 76 #define RX_RING_PI_SHIFT 16 77 #define NHI_RX_RING_SIZE 0x0800c 78 #define RX_RING_BUF_SIZE_SHIFT 16 79 80 /* 81 * One 32-bit status register encodes one status bit per ring indicates that 82 * the watermark from the control descriptor has been reached. 83 */ 84 #define NHI_RX_RING_STATUS 0x19400 85 86 /* 87 * TX and RX Tables. These are 32 byte control fields for each ring. 88 * Only 8 bytes are controllable by the host software, the rest are a 89 * shadow copy by the controller of the current packet that's being 90 * processed. 91 */ 92 #define NHI_TX_RING_TABLE_BASE0 0x19800 93 #define TX_TABLE_INTERVAL_MASK GENMASK(23,0) /* Isoch interval 256ns */ 94 #define TX_TABLE_ITE (1 << 27) /* Isoch tx enable */ 95 #define TX_TABLE_E2E (1 << 28) /* End-to-end flow control */ 96 #define TX_TABLE_NS (1 << 29) /* PCIe No Snoop */ 97 #define TX_TABLE_RAW (1 << 30) /* Raw (1)/frame(0) mode */ 98 #define TX_TABLE_VALID (1 << 31) /* Table entry is valid */ 99 #define NHI_TX_RING_TABLE_TIMESTAMP 0x19804 100 101 #define NHI_RX_RING_TABLE_BASE0 0x29800 102 #define RX_TABLE_TX_E2E_HOPID_SHIFT (1 << 12) 103 #define RX_TABLE_E2E (1 << 28) /* End-to-end flow control */ 104 #define RX_TABLE_NS (1 << 29) /* PCIe No Snoop */ 105 #define RX_TABLE_RAW (1 << 30) /* Raw (1)/frame(0) mode */ 106 #define RX_TABLE_VALID (1 << 31) /* Table entry is valid */ 107 #define NHI_RX_RING_TABLE_BASE1 0x29804 108 #define RX_TABLE_EOF_MASK (1 << 0) 109 #define RX_TABLE_SOF_MASK (1 << 16) 110 111 /* * Interrupt Control/Status Registers 112 * Interrupt Status Register (ISR) 113 * Interrupt status for RX, TX, and Nearly Empty events, one bit per 114 * MSI-X vector. Clear on read. 115 * Only 12 bits per operation, instead of 16? I guess it relates to the 116 * number paths, advertised in the HOST_CAPS register, which is wired to 117 * 0x0c for Alpine Ridge. 118 */ 119 #define NHI_ISR0 0x37800 120 #define ISR0_TX_DESC_SHIFT 0 121 #define ISR0_RX_DESC_SHIFT 12 122 #define ISR0_RX_EMPTY_SHIFT 24 123 #define NHI_ISR1 0x37804 124 #define ISR1_RX_EMPTY_SHIFT 0 125 126 /* * Interrupt Status Clear, corresponds to ISR0/ISR1. Write Only */ 127 #define NHI_ISC0 0x37808 128 #define NHI_ISC1 0x3780c 129 130 /* * Interrupt Status Set, corresponds to ISR0/ISR1. Write Only */ 131 #define NHI_ISS0 0x37810 132 #define NHI_ISS1 0x37814 133 134 /* * Interrupt Mask, corresponds to ISR0/ISR1. Read-Write */ 135 #define NHI_IMR0 0x38200 136 #define NHI_IMR1 0x38204 137 #define IMR_TX_OFFSET 0 138 #define IMR_RX_OFFSET 12 139 #define IMR_NE_OFFSET 24 140 141 /* * Interrupt Mask Clear, corresponds to ISR0/ISR1. Write-only */ 142 #define NHI_IMC0 0x38208 143 #define NHI_IMC1 0x3820c 144 145 /* * Interrupt Mask Set, corresponds to ISR0/ISR1. Write-only */ 146 #define NHI_IMS0 0x38210 147 #define NHI_IMS1 0x38214 148 149 /* 150 * Interrupt Throttle Rate. One 32 bit register per interrupt, 151 * 16 registers for the 16 MSI-X interrupts. Interval is in 256ns 152 * increments. 153 */ 154 #define NHI_ITR0 0x38c00 155 #define ITR_INTERVAL_SHIFT 0 156 #define ITR_COUNTER_SHIFT 16 157 158 /* 159 * Interrupt Vector Allocation. 160 * There are 12 4-bit descriptors for TX, 12 4-bit descriptors for RX, 161 * and 12 4-bit descriptors for Nearly Empty. Each descriptor holds 162 * the numerical value of the MSI-X vector that will receive the 163 * corresponding interrupt. 164 * Bits 0-31 of IVR0 and 0-15 of IVR1 are for TX 165 * Bits 16-31 of IVR1 and 0-31 of IVR2 are for RX 166 * Bits 0-31 of IVR3 and 0-15 of IVR4 are for Nearly Empty 167 */ 168 #define NHI_IVR0 0x38c40 169 #define NHI_IVR1 0x38c44 170 #define NHI_IVR2 0x38c48 171 #define NHI_IVR3 0x38c4c 172 #define NHI_IVR4 0x38c50 173 #define IVR_TX_OFFSET 0 174 #define IVR_RX_OFFSET 12 175 #define IVR_NE_OFFSET 24 176 177 /* Native Host Interface Control registers */ 178 #define NHI_HOST_CAPS 0x39640 179 #define GET_HOST_CAPS_PATHS(val) ((val) & 0x3f) 180 181 /* 182 * This definition comes from the Linux driver. In the USB4 spec, this 183 * register is named Host Interface Control, and the Interrupt Autoclear bit 184 * is at bit17, not bit2. The Linux driver doesn't seem to acknowledge this. 185 */ 186 #define NHI_DMA_MISC 0x39864 187 #define DMA_MISC_INT_AUTOCLEAR (1 << 2) 188 189 /* Thunderbolt firmware mailbox registers */ 190 #define TBT_INMAILDATA 0x39900 191 192 #define TBT_INMAILCMD 0x39904 193 #define INMAILCMD_CMD_MASK 0xff 194 #define INMAILCMD_SAVE_CONNECTED 0x05 195 #define INMAILCMD_DISCONNECT_PCIE 0x06 196 #define INMAILCMD_DRIVER_UNLOAD_DISCONNECT 0x07 197 #define INMAILCMD_DISCONNECT_PORTA 0x10 198 #define INMAILCMD_DISCONNECT_PORTB 0x11 199 #define INMAILCMD_SETMODE_CERT_TB_1ST_DEPTH 0x20 200 #define INMAILCMD_SETMODE_ANY_TB_1ST_DEPTH 0x21 201 #define INMAILCMD_SETMODE_CERT_TB_ANY_DEPTH 0x22 202 #define INMAILCMD_SETMODE_ANY_TB_ANY_DEPTH 0x23 203 #define INMAILCMD_CIO_RESET 0xf0 204 #define INMAILCMD_ERROR (1 << 30) 205 #define INMAILCMD_OPREQ (1 << 31) 206 207 #define TBT_OUTMAILCMD 0x3990c 208 #define OUTMAILCMD_STATUS_BUSY (1 << 12) 209 #define OUTMAILCMD_OPMODE_MASK 0xf00 210 #define OUTMAILCMD_OPMODE_SAFE 0x000 211 #define OUTMAILCMD_OPMODE_AUTH 0x100 212 #define OUTMAILCMD_OPMODE_ENDPOINT 0x200 213 #define OUTMAILCMD_OPMODE_CM_FULL 0x300 214 215 #define TBT_FW_STATUS 0x39944 216 #define FWSTATUS_ENABLE (1 << 0) 217 #define FWSTATUS_INVERT (1 << 1) 218 #define FWSTATUS_START (1 << 2) 219 #define FWSTATUS_CIO_RESET (1 << 30) 220 #define FWSTATUS_CM_READY (1 << 31) 221 222 /* 223 * Link Controller (LC) registers. These are in the Vendor Specific 224 * Extended Capability registers in PCICFG. 225 */ 226 #define AR_LC_MBOX_OUT 0x4c 227 #define ICL_LC_MBOX_OUT 0xf0 228 #define LC_MBOXOUT_VALID (1 << 0) 229 #define LC_MBOXOUT_CMD_SHIFT 1 230 #define LC_MBOXOUT_CMD_MASK (0x7f << LC_MBOXOUT_CMD_SHIFT) 231 #define LC_MBOXOUT_CMD_GO2SX (0x02 << LC_MBOXOUT_CMD_SHIFT) 232 #define LC_MBOXOUT_CMD_GO2SX_NOWAKE (0x03 << LC_MBOXOUT_CMD_SHIFT) 233 #define LC_MBOXOUT_CMD_SXEXIT_TBT (0x04 << LC_MBOXOUT_CMD_SHIFT) 234 #define LC_MBOXOUT_CMD_SXEXIT_NOTBT (0x05 << LC_MBOXOUT_CMD_SHIFT) 235 #define LC_MBOXOUT_CMD_OS_UP (0x06 << LC_MBOXOUT_CMD_SHIFT) 236 #define LC_MBOXOUT_DATA_SHIFT 8 237 #define SET_LC_MBOXOUT_DATA(val) ((val) << LC_MBOXOUT_DATA_SHIFT) 238 239 #define AR_LC_MBOX_IN 0x48 240 #define ICL_LC_MBOX_IN 0xec 241 #define LC_MBOXIN_DONE (1 << 0) 242 #define LC_MBOXIN_CMD_SHIFT 1 243 #define LC_MBOXIN_CMD_MASK (0x7f << LC_MBOXIN_CMD_SHIFT) 244 #define LC_MBOXIN_DATA_SHIFT 8 245 #define GET_LC_MBOXIN_DATA(val) ((val) >> LC_MBOXIN_DATA_SHIFT) 246 247 /* Other Vendor Specific registers */ 248 #define AR_VSCAP_1C 0x1c 249 #define AR_VSCAP_B0 0xb0 250 251 #define ICL_VSCAP_9 0xc8 252 #define ICL_VSCAP9_FWREADY (1 << 31) 253 #define ICL_VSCAP_10 0xcc 254 #define ICL_VSCAP_11 0xd0 255 #define ICL_VSCAP_22 0xfc 256 #define ICL_VSCAP22_FORCEPWR (1 << 1) 257 258 /* * Data structures 259 * Transmit buffer descriptor, 12.3.1. Must be aligned on a 4byte boundary. 260 */ 261 struct nhi_tx_buffer_desc { 262 uint32_t addr_lo; 263 uint32_t addr_hi; 264 uint16_t eof_len; 265 #define TX_BUFFER_DESC_LEN_MASK 0xfff 266 #define TX_BUFFER_DESC_EOF_SHIFT 12 267 uint8_t flags_sof; 268 #define TX_BUFFER_DESC_SOF_MASK 0xf 269 #define TX_BUFFER_DESC_IDE (1 << 4) /* Isoch DMA enable */ 270 #define TX_BUFFER_DESC_DONE (1 << 5) /* Descriptor Done */ 271 #define TX_BUFFER_DESC_RS (1 << 6) /* Request Status/Done */ 272 #define TX_BUFFER_DESC_IE (1 << 7) /* Interrupt Enable */ 273 uint8_t offset; 274 uint32_t payload_time; 275 } __packed; 276 277 /* 278 * Receive buffer descriptor, 12.4.1. 4 byte aligned. This goes into 279 * the descriptor ring, but changes into the _post form when the 280 * controller uses it. 281 */ 282 struct nhi_rx_buffer_desc { 283 uint32_t addr_lo; 284 uint32_t addr_hi; 285 uint16_t reserved0; 286 uint8_t flags; 287 #define RX_BUFFER_DESC_RS (1 << 6) /* Request Status/Done */ 288 #define RX_BUFFER_DESC_IE (1 << 7) /* Interrupt Enable */ 289 uint8_t offset; 290 uint32_t reserved1; 291 } __packed; 292 293 /* 294 * Receive buffer descriptor, after the controller fills it in 295 */ 296 struct nhi_rx_post_desc { 297 uint32_t addr_lo; 298 uint32_t addr_hi; 299 uint16_t eof_len; 300 #define RX_BUFFER_DESC_LEN_MASK 0xfff 301 #define RX_BUFFER_DESC_EOF_SHIFT 12 302 uint8_t flags_sof; 303 #define RX_BUFFER_DESC_SOF_MASK 0xf 304 #define RX_BUFFER_DESC_CRC_ERROR (1 << 4) /* CRC error (frame mode) */ 305 #define RX_BUFFER_DESC_DONE (1 << 5) /* Descriptor Done */ 306 #define RX_BUFFER_DESC_OVERRUN (1 << 6) /* Buffer overrun */ 307 #define RX_BUFFER_DESC_IE (1 << 7) /* Interrupt Enable */ 308 uint8_t offset; 309 uint32_t payload_time; 310 } __packed; 311 312 union nhi_ring_desc { 313 struct nhi_tx_buffer_desc tx; 314 struct nhi_rx_buffer_desc rx; 315 struct nhi_rx_post_desc rxpost; 316 uint32_t dword[4]; 317 }; 318 319 /* Protocol Defined Field (PDF) */ 320 #define PDF_READ 0x01 321 #define PDF_WRITE 0x02 322 #define PDF_NOTIFY 0x03 323 #define PDF_NOTIFY_ACK 0x04 324 #define PDF_HOTPLUG 0x05 325 #define PDF_XDOMAIN_REQ 0x06 326 #define PDF_XDOMAIN_RESP 0x07 327 /* Thunderbolt-only */ 328 #define PDF_CM_EVENT 0x0a 329 #define PDF_CM_REQ 0x0b 330 #define PDF_CM_RESP 0x0c 331 332 #endif /* _NHI_REG_H */ 333