Lines Matching +full:rx +full:- +full:watermark
17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
262 #define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */
263 #define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */
264 #define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */
265 #define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */
266 #define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */
267 #define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */
279 #define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */
289 #define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */
310 /* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */
312 #define PCI_OS_PCIX BIT_30 /* PCI-X Bus */
313 #define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */
315 #define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */
320 #define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */
323 #define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */
324 #define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */
325 #define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */
327 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
330 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
342 /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
345 #define PCI_CTL_SRESET_VMAIN_AV BIT_30 /* Soft Reset for Vmain_av De-Glitch */
346 #define PCI_CTL_BYPASS_VMAIN_AV BIT_29 /* Bypass En. for Vmain_av De-Glitch */
351 #define PCI_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */
360 #define PCI_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */
369 #define PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */
372 #define PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */
380 #define PCI_CF1_REL_PCIE_RESET BIT_21 /* PCI-E reset */
383 #define PCI_CF1_GAT_PCIE_RX_IDLE BIT_19 /* PCI-E Rx Electrical idle */
384 #define PCI_CF1_GAT_PCIE_RESET BIT_18 /* PCI-E Reset */
385 #define PCI_CF1_PRST_PHY_CLKREQ BIT_17 /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
386 #define PCI_CF1_PCIE_RST_CLKREQ BIT_16 /* Enable PCI-E rst generate CLKREQ */
392 /* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */
402 #define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */
407 /* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */
414 /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
441 /* Special ISR registers (Yukon-2 only) */
450 * - completely empty (this is the RAP Block window)
466 #define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */
467 #define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */
499 #define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */
502 /* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */
504 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
525 * Bank 4 - 5
538 /* RSS key registers for Yukon-2 Family */
539 #define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */
545 /* 0x0280 - 0x0292: MAC 2 */
550 * Bank 8 - 15
569 #define Q_WM 0x40 /* 16 bit FIFO Watermark */
593 #define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */
601 * Bank 16 - 23
611 #define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */
612 #define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */
613 #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */
614 #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */
624 /* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
625 #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */
626 #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */
627 #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */
628 #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */
629 #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */
630 #define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */
631 #define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
632 #define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
633 #define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */
634 #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
635 #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
636 #define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
637 #define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
642 /* 0x0c80 - 0x0cbf: MAC 2 */
643 /* 0x0cc0 - 0x0cff: reserved */
648 /* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
652 #define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */
663 /* 0x0d80 - 0x0dbf: MAC 2 */
664 /* 0x0daa - 0x0dff: reserved */
678 /* Polling Unit Registers (Yukon-2 only) */
683 /* ASF Subsystem Registers (Yukon-2 only) */
700 /* Status BMU Registers (Yukon-2 only)*/
711 /* FIFO Control/Status Registers (Yukon-2 only)*/
717 #define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */
718 #define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */
719 /* Level and ISR Timer Registers (Yukon-2 only)*/
736 #define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */
748 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
750 #define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */
757 #define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */
758 #define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */
772 * Bank 32 - 33
777 /* offset to configuration space on Yukon-2 */
786 #define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */
787 #define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */
788 #define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */
789 #define Y2_HW_WOL_OFF BIT_14 /* HW WOL Off (Yukon-EC Ultra A1 only) */
790 #define Y2_ASF_ENABLE BIT_13 /* ASF Unit Enable (YUKON-2 only) */
791 #define Y2_ASF_DISABLE BIT_12 /* ASF Unit Disable (YUKON-2 only) */
792 #define Y2_CLK_RUN_ENA BIT_11 /* CLK_RUN Enable (YUKON-2 only) */
793 #define Y2_CLK_RUN_DIS BIT_10 /* CLK_RUN Disable (YUKON-2 only) */
794 #define Y2_LED_STAT_ON BIT_9 /* Status LED On (YUKON-2 only) */
795 #define Y2_LED_STAT_OFF BIT_8 /* Status LED Off (YUKON-2 only) */
836 #define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */
844 #define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */
866 #define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */
867 #define Y2_IS_PCI_NEXP BIT_24 /* PCI-Express error similar to PCI error */
871 #define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */
877 #define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */
898 #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */
899 #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */
900 #define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */
901 #define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */
902 #define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */
903 #define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */
904 #define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */
905 #define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */
906 #define CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */
907 #define CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */
909 #define CHIP_ID_YUKON_OPT 0xbc /* Chip ID for YUKON-2 Optima */
911 #define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */
912 #define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */
913 #define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */
914 #define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */
916 #define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */
917 #define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */
918 #define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */
923 #define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */
925 #define CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-2 EX A0 */
926 #define CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-2 EX B0 */
928 #define CHIP_REV_YU_SU_A0 0 /* Chip Rev. for Yukon-2 SUPR A0 */
929 #define CHIP_REV_YU_SU_B0 1 /* Chip Rev. for Yukon-2 SUPR B0 */
930 #define CHIP_REV_YU_SU_B1 3 /* Chip Rev. for Yukon-2 SUPR B1 */
932 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
942 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
953 /* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */
954 /* Yukon-EC/FE */
957 /* Yukon-2 */
1048 /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
1095 /* Rx BMU Control / Status Registers (Yukon-2) */
1097 #define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */
1098 #define BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */
1099 #define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */
1100 #define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */
1101 #define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */
1102 #define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */
1103 #define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */
1106 #define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */
1107 #define BMU_START BIT_8 /* Start Rx/Tx Queue */
1121 /* Tx BMU Control / Status Registers (Yukon-2) */
1122 /* Bit 31: same as for Rx */
1126 /* Bit 10..0: same as for Rx */
1129 #define F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/
1130 #define F_TX_CHK_AUTO_ON BIT_30 /* Tx checksum auto-calc On(Yukon EX)*/
1131 #define F_ALM_FULL BIT_28 /* Rx FIFO: almost full */
1134 #define F_WM_REACHED BIT_25 /* Watermark reached */
1135 #define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */
1138 #define F_WATER_MARK 0x0007ff/* Bit 10.. 0: Watermark */
1140 /* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
1152 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
1153 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
1154 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
1155 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
1187 /* Threshold values for Yukon-EC Ultra */
1194 #define MSK_BMU_RX_WM 0x600 /* BMU Rx Watermark */
1195 #define MSK_BMU_TX_WM 0x600 /* BMU Tx Watermark */
1197 #define MSK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */
1207 #define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */
1208 #define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */
1214 /* Minimum RAM Buffer Rx Queue Size */
1250 /* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */
1256 * Marvel-PHY Registers, indirect addressed over GMAC
1262 #define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
1264 #define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
1267 /* Marvel-specific registers */
1268 #define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
1269 #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
1270 /* 0x0b - 0x0e: reserved */
1298 #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */
1301 #define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */
1312 #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */
1314 #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */
1327 #define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */
1328 #define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */
1329 #define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */
1330 #define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */
1331 #define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */
1333 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1342 /***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1349 #define PHY_M_AN_100_T4 BIT_9 /* Not cap. 100Base-T4 (always 0) */
1350 #define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */
1351 #define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */
1352 #define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */
1353 #define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */
1359 #define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */
1360 #define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */
1368 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1372 #define PHY_M_1000C_MPD BIT_10 /* Multi-Port Device */
1378 #define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
1399 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1418 #define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */
1434 #define PHY_M_PS_RX_P_EN BIT_2 /* Rx Pause Enabled */
1446 #define PHY_M_IS_AN_ERROR BIT_15 /* Auto-Negotiation Error */
1450 #define PHY_M_IS_AN_COMPL BIT_11 /* Auto-Negotiation Completed */
1477 #define PHY_M_EC_RX_TIM_CT BIT_7 /* RGMII Rx Timing Control*/
1479 #define PHY_M_EC_FIB_AN_ENA BIT_3 /* Fiber Auto-Neg. Enable (88E1011S only) */
1511 #define PHY_M_LEDC_RX_CTRL BIT_1 /* Rx Activity / Link */
1540 #define PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */
1612 #define PHY_M_FESC_ENA_MCLK BIT_1 /* Enable MAC Rx Clock in sleep mode */
1613 #define PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */
1615 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1623 #define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */
1625 #define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */
1669 #define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */
1689 #define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */
1690 #define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */
1694 #define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */
1695 #define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1707 * MIB Counters base address definitions (low word) -
1719 (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */
1721 (GM_MIB_CNT_BASE + 40) /* Rx spare 1 */
1735 (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */
1737 (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */
1739 (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */
1741 (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */
1743 (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */
1745 (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */
1747 (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */
1749 (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */
1751 (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */
1753 (GM_MIB_CNT_BASE + 168) /* Rx spare 2 */
1755 (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */
1757 (GM_MIB_CNT_BASE + 184) /* Rx spare 3 */
1773 (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */
1775 (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */
1777 (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */
1779 (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */
1781 (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */
1783 (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */
1799 /*----------------------------------------------------------------------------*/
1813 #define GM_GPSR_FC_TX_DIS BIT_13 /* Tx Flow-Control Mode Disabled */
1822 #define GM_GPSR_FC_RX_DIS BIT_2 /* Rx Flow-Control Mode Disabled */
1825 #define GM_GPCR_RMII_PH_ENA BIT_15 /* Enable RMII for PHY (Yukon-FE only) */
1826 #define GM_GPCR_RMII_LB_ENA BIT_14 /* Enable RMII Loopback (Yukon-FE only) */
1827 #define GM_GPCR_FC_TX_DIS BIT_13 /* Disable Tx Flow-Control Mode */
1835 #define GM_GPCR_FC_RX_DIS BIT_4 /* Disable Rx Flow-Control Mode */
1837 #define GM_GPCR_AU_DUP_DIS BIT_2 /* Disable Auto-Update Duplex */
1838 #define GM_GPCR_AU_FCT_DIS BIT_1 /* Disable Auto-Update Flow-C. */
1839 #define GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */
1846 #define GM_TXCR_FORCE_JAM BIT_15 /* Force Jam / Flow-Control */
1851 /* (Yukon-2 only) */
1859 #define GM_RXCR_CRC_DIS BIT_13 /* Remove 4-byte CRC */
1860 #define GM_RXCR_PASS_FC BIT_12 /* Pass FC packets to FIFO (Yukon-1 only) */
1867 /* (Yukon-2 only) */
1881 /* r/o on Yukon, r/w on Yukon-EC */
1885 #define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */
1908 #define GMR_FS_LEN_MSK (0xffff<<16) /* Bit 31..16: Rx Frame Length */
1915 #define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */
1916 #define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */
1921 #define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */
1936 /* Rx GMAC FIFO Flush Mask (default) */
1941 /* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */
1942 /* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */
1943 /* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */
1944 /* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */
1945 /* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */
1946 /* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */
1956 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1973 #define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */
1974 #define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */
1975 #define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */
1976 #define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */
1982 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
1983 #define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */
1984 #define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */
1987 #define TX_JUMBO_ENA BIT_23 /* Enable Jumbo Mode (Yukon-EC Ultra) */
1988 #define TX_JUMBO_DIS BIT_22 /* Disable Jumbo Mode (Yukon-EC Ultra) */
2001 #define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */
2002 #define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */
2009 /* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */
2055 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
2065 #define GMC_BYP_MACSECRX_ON BIT_13 /* Bypass MAC SEC RX */
2066 #define GMC_BYP_MACSECRX_OFF BIT_12 /* Bypass MAC SEC RX Off */
2081 #define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */
2125 bus_write_4((sc)->msk_res[0], (reg), (val))
2127 bus_write_2((sc)->msk_res[0], (reg), (val))
2129 bus_write_1((sc)->msk_res[0], (reg), (val))
2132 bus_read_4((sc)->msk_res[0], (reg))
2134 bus_read_2((sc)->msk_res[0], (reg))
2136 bus_read_1((sc)->msk_res[0], (reg))
2139 bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2141 bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2143 bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2146 bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2148 bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2150 bus_read_1((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2153 CSR_READ_4((sc_if)->msk_softc, (reg))
2155 CSR_READ_2((sc_if)->msk_softc, (reg))
2157 CSR_READ_1((sc_if)->msk_softc, (reg))
2160 CSR_WRITE_4((sc_if)->msk_softc, (reg), (val))
2162 CSR_WRITE_2((sc_if)->msk_softc, (reg), (val))
2164 CSR_WRITE_1((sc_if)->msk_softc, (reg), (val))
2167 ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg))
2182 /* Rx descriptor data structure */
2221 /* YUKON-2 bit values */
2227 /* YUKON-2 Control flags */
2244 /* YUKON-2 Rx/Tx opcodes defines */
2265 /* YUKON-2 STATUS opcodes defines */
2275 /* YUKON-2 SPECIAL opcodes defines */
2305 #define BMU_DEV_0 BIT_26 /* (Rx) Transfer data to Dev0 */
2306 #define BMU_STAT_VAL BIT_25 /* (Rx) Rx Status Valid */
2307 #define BMU_TIST_VAL BIT_24 /* (Rx) Rx TimeStamp Valid */
2316 * Driver uses fixed number of RX buffers such that this limitation
2317 * reduces number of available RX buffers with 64bit DMA so double
2318 * number of RX buffers on platforms that support 64bit DMA. For TX
2357 #define MSK_JUMBO_MTU (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2359 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)
2360 #define MSK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
2412 ((sc)->msk_rdata.msk_tx_ring_paddr + sizeof(struct msk_tx_desc) * (i))
2414 ((sc)->msk_rdata.msk_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i))
2416 ((sc)->msk_rdata.msk_jumbo_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i))
2442 #define MSK_PROC_MAX (MSK_RX_RING_CNT - 1)
2459 /* Rx stats. */
2543 #define MSK_LOCK(_sc) mtx_lock(&(_sc)->msk_mtx)
2544 #define MSK_UNLOCK(_sc) mtx_unlock(&(_sc)->msk_mtx)
2545 #define MSK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->msk_mtx, MA_OWNED)
2546 #define MSK_IF_LOCK(_sc) MSK_LOCK((_sc)->msk_softc)
2547 #define MSK_IF_UNLOCK(_sc) MSK_UNLOCK((_sc)->msk_softc)
2548 #define MSK_IF_LOCK_ASSERT(_sc) MSK_LOCK_ASSERT((_sc)->msk_softc)
2550 #define MSK_USECS(sc, us) ((sc)->msk_clock * (us))
2579 uint32_t msk_rxq; /* Rx. Qeueue offset */