| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_udma_regs_gen.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
100 /* [0x0] Target-ID control */
102 /* [0x4] TX queue 0/1 Target-ID */
104 /* [0x8] TX queue 2/3 Target-ID */
106 /* [0xc] RX queue 0/1 Target-ID */
108 /* [0x10] RX queue 2/3 Target-ID */
112 /* [0x0] TX queue 0/1 Target-Address */
114 /* [0x4] TX queue 2/3 Target-Address */
116 /* [0x8] RX queue 0/1 Target-Address */
118 /* [0xc] RX queue 2/3 Target-Address */
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| H A D | al_hal_serdes_internal_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
47 * RX and TX lane hard reset
48 * 0 - Hard reset is asserted
49 * 1 - Hard reset is de-asserted
57 * RX and TX lane hard reset control
58 * 0 - Hard reset is taken from the interface pins
59 * 1 - Hard reset is taken from registers
66 /* RX lane power state control */
84 /* RX lane word width */
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| H A D | al_hal_serdes_hssp_internal_regs.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
46 * RX and TX lane hard reset
47 * 0 - Hard reset is asserted
48 * 1 - Hard reset is de-asserted
56 * RX and TX lane hard reset control
57 * 0 - Hard reset is taken from the interface pins
58 * 1 - Hard reset is taken from registers
65 /* RX lane power state control */
83 /* RX lane word width */
103 /* RX lane rate select */
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| H A D | al_hal_serdes_interface.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
101 * Transmits the untimed, partial equalized RX signal out the transmit
114 * Loops back the TX driver IO signal to the RX IO pins
129 /** Loops TX data (to PMA) to RX path (instead of PMA data) */
178 * Tx de-emphasis parameters
183 AL_SERDES_TX_DEEMP_C_MINUS, /*< c(-1) */
196 * Transmit Amplitude control signal. Used to define the full-scale
198 * 000 - Not Supported
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| /freebsd/sys/dev/bfe/ |
| H A D | if_bfereg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 #define BFE_PFE 0x00000080 /* Pattern Filtering Enable */
41 #define BFE_PME 0x00001000 /* PHY Mode Enable */
42 #define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */
46 #define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */
58 #define BFE_ISTAT_RX 0x00010000 /* RX Interrupt */
71 #define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */
79 #define BFE_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */
87 #define BFE_TX_CTRL_ENABLE 0x00000001 /* Enable */
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| /freebsd/sys/dev/ath/ath_hal/ar5210/ |
| H A D | ar5210reg.h | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2004 Atheros Communications, Inc.
24 * Processor for IEEE 802.11a 5-GHz Wireless LANs.
37 #define AR_RXDP 0x000c /* RX queue descriptor ptr register */
41 #define AR_IER 0x0024 /* Interrupt global enable register */
45 #define AR_RXCFG 0x0034 /* RX configuration register */
48 #define AR_RXNOFRM 0x0048 /* RX no frame timeout register */
50 #define AR_RPGTO 0x0050 /* RX frame gap timeout register */
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| /freebsd/sys/dev/cas/ |
| H A D | if_casreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * from: FreeBSD: if_gemreg.h 174987 2007-12-30 01:32:03Z marius
43 #define CAS_INF_BURST 0x0008 /* infinite burst enable */
53 #define CAS_BIM_LDEV_OEN 0x1020 /* BIM local device output enable */
73 #define CAS_CAW_RX_WGHT_MASK 0x00000003 /* RX DMA factor for... */
75 #define CAS_CAW_TX_WGHT_MASK 0x0000000c /* RX DMA factor for... */
84 * Bits 0-9 of CAS_STATUS auto-clear when read. CAS_CLEAR_ALIAS specifies
85 * which of bits 0-9 auto-clear when reading CAS_STATUS_ALIAS.
91 #define CAS_INTR_RX_DONE 0x00000010 /* >=1 RX frames transferred. */
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| /freebsd/sys/dev/vge/ |
| H A D | if_vgereg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
54 #define VGE_RXCTL 0x06 /* RX control register */
82 #define VGE_RXHOSTERR 0x23 /* RX host error status */
87 #define VGE_RXQCSRS 0x32 /* RX queue ctl/status set */
89 #define VGE_RXQCSRC 0x36 /* RX queue ctl/status clear */
90 #define VGE_RXDESC_ADDR_LO 0x38 /* RX desc base addr (lo 32 bits) */
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| /freebsd/sys/dev/e1000/ |
| H A D | e1000_defines.h | 2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
44 #define E1000_WUC_APME 0x00000001 /* APM Enable */
45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
51 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
54 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
55 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
56 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
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| H A D | e1000_82575.h | 2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
46 * These entries are also used for MAC-based filtering.
93 #define E1000_ADV_DCMD_TSE 0x80 /* TCP Seg enable */
177 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
178 #define E1000_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
226 #define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
250 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
251 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
259 /* 1st & Last TSO-full iSCSI PDU*/
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| /freebsd/sys/dev/igc/ |
| H A D | igc_defines.h | 1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
16 #define IGC_WUC_APME 0x00000001 /* APM Enable */
17 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
23 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
24 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
25 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
26 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
27 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
28 #define IGC_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
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| /freebsd/sys/contrib/alpine-hal/eth/ |
| H A D | al_hal_eth.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
61 /* *INDENT-OFF* */
65 /* *INDENT-ON* */
97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200)
174 /** Tx to Rx switching decision type */
182 /** Tx to Rx VLAN ID selection type */
192 /** Rx descriptor configurations */
193 /* Note: when selecting rx descriptor field to inner packet, then that field
194 * will be set according to inner packet when packet is tunneled, for non-tunneled
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| H A D | al_hal_eth_ec_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
62 /* [0x4] Enable modules operation. */
64 /* [0x8] Enable FIFO operation on the EC side. */
72 /* [0x18] Enable modules operation (extended operations). */
86 /* [0x0] Rx FIFO input controller configuration 1 */
88 /* [0x4] Rx FIFO input controller configuration 2 */
90 /* [0x8] Threshold to start reading packet from the Rx FIFO */
92 /* [0xc] Threshold to stop writing packet to the Rx FIFO */
96 /* [0x14] Rx FIFO input controller loopback FIFO configuratio ... */
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| /freebsd/share/man/man4/ |
| H A D | ena.4 | 1 .\" SPDX-License-Identifier: BSD-2-Clause
3 .\" Copyright (c) 2015-2024 Amazon.com, Inc. or its affiliates.
40 .Bd -ragged -offset indent
47 .Bd -literal -offset indent
58 The driver supports a range of ENA devices, is link-speed independent
62 Some ENA devices support SR-IOV.
63 This driver is used for both the SR-IOV Physical Function (PF) and Virtual
66 The ENA devices enable high speed and low overhead network traffic
67 processing by providing multiple Tx/Rx queue pairs (the maximum number
68 is advertised by the device via the Admin Queue), a dedicated MSI-X
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| /freebsd/sys/dev/ic/ |
| H A D | z8530.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
57 #define WR_MCB1 10 /* Miscellaneous Control Bits (part 1 :-). */
61 #define WR_MCB2 14 /* Miscellaneous Control Bits (part 2 :-). */
90 #define BES_RXA 0x01 /* Rx Available. */
93 #define CMC_XTAL 0x80 /* -RTxC connects to quartz crystal. */
94 #define CMC_RC_DPLL 0x60 /* Rx Clock from DPLL. */
95 #define CMC_RC_BRG 0x40 /* Rx Clock from BRG. */
96 #define CMC_RC_TRXC 0x20 /* Rx Clock from -TRxC. */
97 #define CMC_RC_RTXC 0x00 /* Rx Clock from -RTxC. */
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | dwc3.txt | 3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
20 "samsung,exynos5250-dwusb3"
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| H A D | snps,dwc3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 -
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| /freebsd/sys/dev/le/ |
| H A D | lancereg.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
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| /freebsd/sys/arm/allwinner/ |
| H A D | aw_cir.c | 1 /*-
49 #define READ(_sc, _r) bus_read_4((_sc)->res[0], (_r))
50 #define WRITE(_sc, _r, _v) bus_write_4((_sc)->res[0], (_r), (_v))
54 /* Global Enable */
56 /* RX enable */
58 /* CIR mode enable */
61 /* RX Config Reg */
66 /* RX Data */
69 /* RX Interrupt Control */
71 /* RX FIFO Overflow */
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| /freebsd/sys/dev/msk/ |
| H A D | if_mskreg.h | 17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
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| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_recv.c | 56 * Set Receive Enable bits.
65 * Set the RX abort bit.
74 if ( AH9300(ah)->ah_reset_reason == HAL_RESET_BBPANIC ){ in ar9300_set_rx_abort()
75 /* depending upon the BB panic status, rx state may not return to 0, in ar9300_set_rx_abort()
83 /* Wait for Rx state to return to 0 */ in ar9300_set_rx_abort()
85 /* abort: chip rx failed to go idle in 10 ms */ in ar9300_set_rx_abort()
90 "%s: rx failed to go idle in 10 ms RXSM=0x%x\n", in ar9300_set_rx_abort()
130 /* wait for Rx DMA state machine to become idle */ in ar9300_stop_dma_receive()
140 /* Wait for rx enable bit to go low */ in ar9300_stop_dma_receive()
141 for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) { in ar9300_stop_dma_receive()
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| /freebsd/sys/dev/smc/ |
| H A D | if_smcreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
39 #define TCR_TXENA 0x0001 /* Enable/disable transmitter */
43 #define TCR_NOCRC 0x0100 /* Disable/enable CRC */
45 #define TCR_FDUPLX 0x0800 /* Enable/disable full duplex */
69 #define RCR_RX_ABORT 0x0001 /* RX aborted */
70 #define RCR_PRMS 0x0002 /* Enable/disable promiscuous mode */
72 #define RCR_RXEN 0x0100 /* Enable/disable receiver */
73 #define RCR_STRIP_CRC 0x0200 /* Strip CRC from RX packets */
74 #define RCR_ABORT_ENB 0x2000 /* Abort RX on collision */
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | xlnx,axi-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-etherne
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| /freebsd/sys/dev/uart/ |
| H A D | uart_dev_mvebu.c | 1 /*-
55 #define CTRL_RX_FIFO_RST (1 << 14) /* RX FIFO Reset */
56 #define CTRL_ST_MIRR_EN (1 << 13) /* Status Mirror Enable */
57 #define CTRL_LPBK_EN (1 << 12) /* Loopback Mode Enable */
59 #define CTRL_PAR_EN (1 << 10) /* Parity Enable */
61 #define CTRL_TX_HALF_INT (1 << 8) /* TX Half-Full Interrupt Enable */
62 #define CTRL_RX_HALF_INT (1 << 7) /* RX Half-Full Interrupt Enable */
63 #define CTRL_TX_EMPT_INT (1 << 6) /* TX Empty Interrupt Enable */
64 #define CTRL_TX_RDY_INT (1 << 5) /* TX Ready Interrupt Enable */
65 #define CTRL_RX_RDY_INT (1 << 4) /* RX Ready Interrupt Enable */
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| /freebsd/sys/dev/mwl/ |
| H A D | mwlhal.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
39 #define MWL_MBSS_SUPPORT /* enable multi-bss support */
85 * Query whether multi-bss support is available/enabled.
132 cause = bus_space_read_4(mh->mh_iot, mh->mh_ioh, in mwl_hal_getisr()
138 bus_space_write_4(mh->mh_iot, mh->mh_ioh, in mwl_hal_getisr()
139 MACREG_REG_A2H_INTERRUPT_CAUSE, cause &~ mh->mh_imask); in mwl_hal_getisr()
140 (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, in mwl_hal_getisr()
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