Lines Matching +full:rx +full:- +full:enable
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
44 #define E1000_WUC_APME 0x00000001 /* APM Enable */
45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
51 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
54 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
55 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
56 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
57 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
58 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
80 #define E1000_CTRL_EXT_SDLPE 0X00040000 /* SerDes Low Power Enable */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
132 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
173 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
175 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
178 /* Enable MAC address filtering */
180 /* Enable MNG packets to host memory */
190 #define E1000_RCTL_EN 0x00000002 /* enable */
192 #define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */
193 #define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */
194 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
199 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
204 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
206 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
207 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
208 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
209 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
211 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
212 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
213 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
214 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
215 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
259 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
262 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
264 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
273 #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */
278 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
285 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
286 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
287 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
289 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
341 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
342 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
344 /* Constants used to interpret the masked PCI-X bus speed. */
345 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
346 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
347 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
366 /* 1000/H is not supported, nor spec-compliant. */
405 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
412 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
417 #define E1000_TCTL_EN 0x00000002 /* enable Tx */
421 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
425 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
435 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
436 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
475 /* The datasheet maximum supported RX size is 9.5KB (9728 bytes) */
524 /* Uncorrectable/correctable ECC Error counts and enable bits */
547 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
548 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
549 #define E1000_ICR_RXO 0x00000040 /* Rx overrun */
550 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
552 #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
565 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
566 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
581 #define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */
583 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */
586 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
587 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
588 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
589 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
598 #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
622 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
623 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
624 #define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */
625 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
631 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
632 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
641 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
642 #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
643 #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
644 #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
654 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
655 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
658 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
659 #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
660 #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
661 #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
681 /* Enable the counting of descriptors still to be processed. */
728 /* Loop limit on how long we wait for auto-negotiation to complete */
745 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
752 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
761 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
769 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
770 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
776 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
814 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
823 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
834 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
865 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
866 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
870 #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
925 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
930 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
977 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */
987 /* 1000BASE-T Control Register */
1003 /* 1000BASE-T Status Register */
1026 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1027 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1047 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1193 /* NVM Commands - Microwire */
1197 #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */
1200 /* NVM Commands - SPI */
1204 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1205 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
1232 /* PCI/PCI-X/PCI-EX Config space */
1256 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1307 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1318 * 1 = 50-80M
1319 * 2 = 80-110M
1320 * 3 = 110-140M
1380 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
1383 * 15-5: page
1384 * 4-0: register offset
1402 /* Page 193 - Port Control Registers */
1407 /* Page 194 - KMRN Registers */
1451 /* Tx Rate-Scheduler Config fields */
1461 /* DMA Coalescing Rx Threshold */
1467 #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
1468 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1476 /* Rx Traffic Rate Threshold */
1478 /* Rx packet rate in current window */
1481 /* DMA Coal Rx Traffic Current Count */
1484 /* Flow ctrl Rx Threshold High val */
1490 #define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
1491 #define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */
1500 #define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */
1503 #define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */
1505 #define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */
1506 #define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */