Lines Matching +full:rx +full:- +full:enable

2   SPDX-License-Identifier: BSD-3-Clause
4   Copyright (c) 2001-2020, Intel Corporation
46  * These entries are also used for MAC-based filtering.
93 #define E1000_ADV_DCMD_TSE	0x80 /* TCP Seg enable */
177 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
178 #define E1000_IMIR_PORT_IM_EN	0x00010000  /* TCP port enable */
226 #define E1000_RXDADV_PKTTYPE_ETQF_SHIFT	4 /* Right-shift 4 bits */
250 #define E1000_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
251 #define E1000_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
259 /* 1st & Last TSO-full iSCSI PDU*/
271 #define E1000_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
272 #define E1000_RXDCTL_SWFLSH		0x04000000 /* Rx Desc. wbk flushing */
275 #define E1000_DCA_CTRL_DCA_ENABLE	0x00000000 /* DCA Enable */
281 #define E1000_DCA_RXCTRL_CPUID_MASK	0x0000001F /* Rx CPUID Mask */
282 #define E1000_DCA_RXCTRL_DESC_DCA_EN	(1 << 5) /* DCA Rx Desc enable */
283 #define E1000_DCA_RXCTRL_HEAD_DCA_EN	(1 << 6) /* DCA Rx Desc header ena */
284 #define E1000_DCA_RXCTRL_DATA_DCA_EN	(1 << 7) /* DCA Rx Desc payload ena */
285 #define E1000_DCA_RXCTRL_DESC_RRO_EN	(1 << 9) /* DCA Rx Desc Relax Order */
288 #define E1000_DCA_TXCTRL_DESC_DCA_EN	(1 << 5) /* DCA Tx Desc enable */
294 #define E1000_DCA_RXCTRL_CPUID_MASK_82576	0xFF000000 /* Rx CPUID Mask */
296 #define E1000_DCA_RXCTRL_CPUID_SHIFT_82576	24 /* Rx CPUID */
299 #define E1000_ICR_LSECPNS	0x00000020 /* PN threshold - server */
300 #define E1000_IMS_LSECPNS	E1000_ICR_LSECPNS /* PN threshold - server */
301 #define E1000_ICS_LSECPNS	E1000_ICR_LSECPNS /* PN threshold - server */
325 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN	(1U << 31)  /* global VF LB enable */
339 #define E1000_VMOLR_RSSE	0x00020000 /* Enable RSS */
345 #define E1000_VMOLR_STRVLAN	0x40000000 /* Vlan stripping enable */
346 #define E1000_VMOLR_STRCRC	0x80000000 /* CRC stripping enable */
348 #define E1000_VMOLR_VPE		0x00800000 /* VLAN promiscuous enable */
349 #define E1000_VMOLR_UPE		0x20000000 /* Unicast promisuous enable */
350 #define E1000_DVMOLR_HIDVLAN	0x20000000 /* Vlan hiding enable */
351 #define E1000_DVMOLR_STRVLAN	0x40000000 /* Vlan stripping enable */
352 #define E1000_DVMOLR_STRCRC	0x80000000 /* CRC stripping enable */
354 #define E1000_PBRWAC_WALPB	0x00000007 /* Wrap around event on LAN Rx PB */
355 #define E1000_PBRWAC_PBE	0x00000008 /* Rx packet buffer empty */
391 /* Rx packet buffer size defines */
393 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
394 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf);
395 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);