1cf4c5a53SSam Leffler /*-
2*4d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause
3718cf2ccSPedro F. Giffuni *
4cf4c5a53SSam Leffler * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
5cf4c5a53SSam Leffler * Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
6cf4c5a53SSam Leffler * All rights reserved.
7cf4c5a53SSam Leffler *
8cf4c5a53SSam Leffler * Redistribution and use in source and binary forms, with or without
9cf4c5a53SSam Leffler * modification, are permitted provided that the following conditions
10cf4c5a53SSam Leffler * are met:
11cf4c5a53SSam Leffler * 1. Redistributions of source code must retain the above copyright
12cf4c5a53SSam Leffler * notice, this list of conditions and the following disclaimer,
13cf4c5a53SSam Leffler * without modification.
14cf4c5a53SSam Leffler * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15cf4c5a53SSam Leffler * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
16cf4c5a53SSam Leffler * redistribution must be conditioned upon including a substantially
17cf4c5a53SSam Leffler * similar Disclaimer requirement for further binary redistribution.
18cf4c5a53SSam Leffler *
19cf4c5a53SSam Leffler * NO WARRANTY
20cf4c5a53SSam Leffler * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21cf4c5a53SSam Leffler * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22cf4c5a53SSam Leffler * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
23cf4c5a53SSam Leffler * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
24cf4c5a53SSam Leffler * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
25cf4c5a53SSam Leffler * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26cf4c5a53SSam Leffler * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27cf4c5a53SSam Leffler * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
28cf4c5a53SSam Leffler * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29cf4c5a53SSam Leffler * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30cf4c5a53SSam Leffler * THE POSSIBILITY OF SUCH DAMAGES.
31cf4c5a53SSam Leffler */
32cf4c5a53SSam Leffler
33cf4c5a53SSam Leffler #ifndef _MWL_HAL_H_
34cf4c5a53SSam Leffler #define _MWL_HAL_H_
35cf4c5a53SSam Leffler /*
36cf4c5a53SSam Leffler * Hardware Access Layer for Marvell Wireless Devices.
37cf4c5a53SSam Leffler */
38cf4c5a53SSam Leffler
39cf4c5a53SSam Leffler #define MWL_MBSS_SUPPORT /* enable multi-bss support */
40cf4c5a53SSam Leffler
41cf4c5a53SSam Leffler /*
42cf4c5a53SSam Leffler * Define total number of TX queues in the shared memory.
43cf4c5a53SSam Leffler * This count includes the EDCA queues, Block Ack queues, and HCCA queues
44cf4c5a53SSam Leffler * In addition to this, there could be a management packet queue some
45cf4c5a53SSam Leffler * time in the future
46cf4c5a53SSam Leffler */
47cf4c5a53SSam Leffler #define MWL_NUM_EDCA_QUEUES 4
48cf4c5a53SSam Leffler #define MWL_NUM_HCCA_QUEUES 0
49cf4c5a53SSam Leffler #define MWL_NUM_BA_QUEUES 0
50cf4c5a53SSam Leffler #define MWL_NUM_MGMT_QUEUES 0
517850fa71SSam Leffler #define MWL_NUM_ACK_QUEUES 0
52cf4c5a53SSam Leffler #define MWL_NUM_TX_QUEUES \
53cf4c5a53SSam Leffler (MWL_NUM_EDCA_QUEUES + MWL_NUM_HCCA_QUEUES + MWL_NUM_BA_QUEUES + \
547850fa71SSam Leffler MWL_NUM_MGMT_QUEUES + MWL_NUM_ACK_QUEUES)
55cf4c5a53SSam Leffler #define MWL_MAX_RXWCB_QUEUES 1
56cf4c5a53SSam Leffler
57cf4c5a53SSam Leffler #define MWL_MAX_SUPPORTED_RATES 12
58cf4c5a53SSam Leffler #define MWL_MAX_SUPPORTED_MCS 32
59cf4c5a53SSam Leffler
60cf4c5a53SSam Leffler typedef enum {
61cf4c5a53SSam Leffler MWL_HAL_OK
62cf4c5a53SSam Leffler } MWL_HAL_STATUS;
63cf4c5a53SSam Leffler
64cf4c5a53SSam Leffler /*
65cf4c5a53SSam Leffler * Transmit queue assignment.
66cf4c5a53SSam Leffler */
67cf4c5a53SSam Leffler enum {
68cf4c5a53SSam Leffler MWL_WME_AC_BK = 0, /* background access category */
69cf4c5a53SSam Leffler MWL_WME_AC_BE = 1, /* best effort access category*/
70cf4c5a53SSam Leffler MWL_WME_AC_VI = 2, /* video access category */
71cf4c5a53SSam Leffler MWL_WME_AC_VO = 3, /* voice access category */
72cf4c5a53SSam Leffler };
73cf4c5a53SSam Leffler
74cf4c5a53SSam Leffler struct mwl_hal {
75cf4c5a53SSam Leffler bus_space_handle_t mh_ioh; /* BAR 1 copied from softc */
76cf4c5a53SSam Leffler bus_space_tag_t mh_iot;
77cf4c5a53SSam Leffler uint32_t mh_imask; /* interrupt mask */
78cf4c5a53SSam Leffler /* remainder is opaque to driver */
79cf4c5a53SSam Leffler };
80dd8a5c35SAdrian Chadd struct mwl_hal *mwl_hal_attach(device_t dev, uint16_t devid,
81cf4c5a53SSam Leffler bus_space_handle_t ioh, bus_space_tag_t iot, bus_dma_tag_t tag);
82cf4c5a53SSam Leffler void mwl_hal_detach(struct mwl_hal *);
83cf4c5a53SSam Leffler
84cf4c5a53SSam Leffler /*
85cf4c5a53SSam Leffler * Query whether multi-bss support is available/enabled.
86cf4c5a53SSam Leffler */
87cf4c5a53SSam Leffler int mwl_hal_ismbsscapable(struct mwl_hal *);
88cf4c5a53SSam Leffler
89cf4c5a53SSam Leffler typedef enum {
90cf4c5a53SSam Leffler MWL_HAL_AP,
91cf4c5a53SSam Leffler MWL_HAL_STA, /* infrastructure mode */
92cf4c5a53SSam Leffler MWL_HAL_IBSS /* ibss/adhoc mode */
93cf4c5a53SSam Leffler } MWL_HAL_BSSTYPE;
94cf4c5a53SSam Leffler struct mwl_hal_vap;
95cf4c5a53SSam Leffler
96cf4c5a53SSam Leffler struct mwl_hal_vap *mwl_hal_newvap(struct mwl_hal *, MWL_HAL_BSSTYPE,
97cf4c5a53SSam Leffler const uint8_t mac[6]);
98cf4c5a53SSam Leffler void mwl_hal_delvap(struct mwl_hal_vap *);
99cf4c5a53SSam Leffler
100cf4c5a53SSam Leffler enum {
101cf4c5a53SSam Leffler MWL_HAL_DEBUG_SENDCMD = 0x00000001,
102cf4c5a53SSam Leffler MWL_HAL_DEBUG_CMDDONE = 0x00000002,
103cf4c5a53SSam Leffler MWL_HAL_DEBUG_IGNHANG = 0x00000004,
104cf4c5a53SSam Leffler };
105cf4c5a53SSam Leffler void mwl_hal_setdebug(struct mwl_hal *, int);
106cf4c5a53SSam Leffler int mwl_hal_getdebug(struct mwl_hal *);
107cf4c5a53SSam Leffler
108cf4c5a53SSam Leffler typedef struct {
109cf4c5a53SSam Leffler uint16_t freqLow, freqHigh;
110cf4c5a53SSam Leffler int nchannels;
111cf4c5a53SSam Leffler struct mwl_hal_channel {
112cf4c5a53SSam Leffler uint16_t freq; /* channel center */
113cf4c5a53SSam Leffler uint8_t ieee; /* channel number */
114cf4c5a53SSam Leffler int8_t maxTxPow; /* max tx power (dBm) */
115cf4c5a53SSam Leffler uint8_t targetPowers[4];/* target powers (dBm) */
116cf4c5a53SSam Leffler #define MWL_HAL_MAXCHAN 40
117cf4c5a53SSam Leffler } channels[MWL_HAL_MAXCHAN];
118cf4c5a53SSam Leffler } MWL_HAL_CHANNELINFO;
119cf4c5a53SSam Leffler int mwl_hal_getchannelinfo(struct mwl_hal *, int band, int chw,
120cf4c5a53SSam Leffler const MWL_HAL_CHANNELINFO **);
121cf4c5a53SSam Leffler
122cf4c5a53SSam Leffler /*
123cf4c5a53SSam Leffler * Return the current ISR setting and clear the cause.
124cf4c5a53SSam Leffler */
125cf4c5a53SSam Leffler static __inline void
mwl_hal_getisr(struct mwl_hal * mh,uint32_t * status)126cf4c5a53SSam Leffler mwl_hal_getisr(struct mwl_hal *mh, uint32_t *status)
127cf4c5a53SSam Leffler {
128cf4c5a53SSam Leffler #define MACREG_REG_A2H_INTERRUPT_CAUSE 0x00000C30 // (From ARM to host)
129cf4c5a53SSam Leffler #define MACREG_REG_INT_CODE 0x00000C14
130cf4c5a53SSam Leffler uint32_t cause;
131cf4c5a53SSam Leffler
132cf4c5a53SSam Leffler cause = bus_space_read_4(mh->mh_iot, mh->mh_ioh,
133cf4c5a53SSam Leffler MACREG_REG_A2H_INTERRUPT_CAUSE);
134cf4c5a53SSam Leffler if (cause == 0xffffffff) { /* card removed */
135cf4c5a53SSam Leffler cause = 0;
136cf4c5a53SSam Leffler } else if (cause != 0) {
137cf4c5a53SSam Leffler /* clear cause bits */
138cf4c5a53SSam Leffler bus_space_write_4(mh->mh_iot, mh->mh_ioh,
139cf4c5a53SSam Leffler MACREG_REG_A2H_INTERRUPT_CAUSE, cause &~ mh->mh_imask);
140cf4c5a53SSam Leffler (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh,
141cf4c5a53SSam Leffler MACREG_REG_INT_CODE);
142cf4c5a53SSam Leffler cause &= mh->mh_imask;
143cf4c5a53SSam Leffler }
144cf4c5a53SSam Leffler *status = cause;
145cf4c5a53SSam Leffler #undef MACREG_REG_INT_CODE
146cf4c5a53SSam Leffler #undef MACREG_REG_A2H_INTERRUPT_CAUSE
147cf4c5a53SSam Leffler }
148cf4c5a53SSam Leffler
149cf4c5a53SSam Leffler void mwl_hal_intrset(struct mwl_hal *mh, uint32_t mask);
150cf4c5a53SSam Leffler
151cf4c5a53SSam Leffler /*
152cf4c5a53SSam Leffler * Kick the firmware to tell it there are new tx descriptors
153cf4c5a53SSam Leffler * for processing. The driver says what h/w q has work in
154cf4c5a53SSam Leffler * case the f/w ever gets smarter.
155cf4c5a53SSam Leffler */
156cf4c5a53SSam Leffler static __inline void
mwl_hal_txstart(struct mwl_hal * mh,int qnum)157cf4c5a53SSam Leffler mwl_hal_txstart(struct mwl_hal *mh, int qnum)
158cf4c5a53SSam Leffler {
159cf4c5a53SSam Leffler #define MACREG_REG_H2A_INTERRUPT_EVENTS 0x00000C18 // (From host to ARM)
160cf4c5a53SSam Leffler #define MACREG_H2ARIC_BIT_PPA_READY 0x00000001 // bit 0
161cf4c5a53SSam Leffler #define MACREG_REG_INT_CODE 0x00000C14
162cf4c5a53SSam Leffler
163cf4c5a53SSam Leffler bus_space_write_4(mh->mh_iot, mh->mh_ioh,
164cf4c5a53SSam Leffler MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_PPA_READY);
165cf4c5a53SSam Leffler (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, MACREG_REG_INT_CODE);
166cf4c5a53SSam Leffler #undef MACREG_REG_INT_CODE
167cf4c5a53SSam Leffler #undef MACREG_H2ARIC_BIT_PPA_READY
168cf4c5a53SSam Leffler #undef MACREG_REG_H2A_INTERRUPT_EVENTS
169cf4c5a53SSam Leffler }
170cf4c5a53SSam Leffler
171cf4c5a53SSam Leffler void mwl_hal_cmddone(struct mwl_hal *mh);
172cf4c5a53SSam Leffler
173cf4c5a53SSam Leffler typedef struct {
174cf4c5a53SSam Leffler uint32_t FreqBand : 6,
175cf4c5a53SSam Leffler #define MWL_FREQ_BAND_2DOT4GHZ 0x1
176cf4c5a53SSam Leffler #define MWL_FREQ_BAND_5GHZ 0x4
177cf4c5a53SSam Leffler ChnlWidth: 5,
178cf4c5a53SSam Leffler #define MWL_CH_10_MHz_WIDTH 0x1
179cf4c5a53SSam Leffler #define MWL_CH_20_MHz_WIDTH 0x2
180cf4c5a53SSam Leffler #define MWL_CH_40_MHz_WIDTH 0x4
181cf4c5a53SSam Leffler ExtChnlOffset: 2,
182cf4c5a53SSam Leffler #define MWL_EXT_CH_NONE 0x0
183cf4c5a53SSam Leffler #define MWL_EXT_CH_ABOVE_CTRL_CH 0x1
184cf4c5a53SSam Leffler #define MWL_EXT_CH_BELOW_CTRL_CH 0x3
185cf4c5a53SSam Leffler : 19; /* reserved */
186cf4c5a53SSam Leffler } MWL_HAL_CHANNEL_FLAGS;
187cf4c5a53SSam Leffler
188cf4c5a53SSam Leffler typedef struct {
189cf4c5a53SSam Leffler uint32_t channel;
190cf4c5a53SSam Leffler MWL_HAL_CHANNEL_FLAGS channelFlags;
191cf4c5a53SSam Leffler } MWL_HAL_CHANNEL;
192cf4c5a53SSam Leffler
193cf4c5a53SSam Leffler /*
194cf4c5a53SSam Leffler * Get Hardware/Firmware capabilities.
195cf4c5a53SSam Leffler */
196cf4c5a53SSam Leffler struct mwl_hal_hwspec {
197cf4c5a53SSam Leffler uint8_t hwVersion; /* version of the HW */
198cf4c5a53SSam Leffler uint8_t hostInterface; /* host interface */
199cf4c5a53SSam Leffler uint16_t maxNumWCB; /* max # of WCB FW handles */
200cf4c5a53SSam Leffler uint16_t maxNumMCAddr; /* max # of mcast addresses FW handles*/
201cf4c5a53SSam Leffler uint16_t maxNumTxWcb; /* max # of tx descs per WCB */
202cf4c5a53SSam Leffler uint8_t macAddr[6]; /* MAC address programmed in HW */
203cf4c5a53SSam Leffler uint16_t regionCode; /* EEPROM region code */
204cf4c5a53SSam Leffler uint16_t numAntennas; /* Number of antenna used */
205cf4c5a53SSam Leffler uint32_t fwReleaseNumber; /* firmware release number */
206cf4c5a53SSam Leffler uint32_t wcbBase0;
207cf4c5a53SSam Leffler uint32_t rxDescRead;
208cf4c5a53SSam Leffler uint32_t rxDescWrite;
209cf4c5a53SSam Leffler uint32_t ulFwAwakeCookie;
2107850fa71SSam Leffler uint32_t wcbBase[MWL_NUM_TX_QUEUES - MWL_NUM_ACK_QUEUES];
211cf4c5a53SSam Leffler };
212cf4c5a53SSam Leffler int mwl_hal_gethwspecs(struct mwl_hal *mh, struct mwl_hal_hwspec *);
213cf4c5a53SSam Leffler
214cf4c5a53SSam Leffler /*
215cf4c5a53SSam Leffler * Supply tx/rx dma-related settings to the firmware.
216cf4c5a53SSam Leffler */
217cf4c5a53SSam Leffler struct mwl_hal_txrxdma {
218cf4c5a53SSam Leffler uint32_t maxNumWCB; /* max # of WCB FW handles */
219cf4c5a53SSam Leffler uint32_t maxNumTxWcb; /* max # of tx descs per WCB */
220cf4c5a53SSam Leffler uint32_t rxDescRead;
221cf4c5a53SSam Leffler uint32_t rxDescWrite;
2227850fa71SSam Leffler uint32_t wcbBase[MWL_NUM_TX_QUEUES - MWL_NUM_ACK_QUEUES];
223cf4c5a53SSam Leffler };
224cf4c5a53SSam Leffler int mwl_hal_sethwdma(struct mwl_hal *mh, const struct mwl_hal_txrxdma *);
225cf4c5a53SSam Leffler
226cf4c5a53SSam Leffler /*
227cf4c5a53SSam Leffler * Get Hardware Statistics.
228cf4c5a53SSam Leffler *
229cf4c5a53SSam Leffler * Items marked with ! are deprecated and not ever updated. In
230cf4c5a53SSam Leffler * some cases this is because work has been moved to the host (e.g.
231cf4c5a53SSam Leffler * rx defragmentation).
232cf4c5a53SSam Leffler */
233cf4c5a53SSam Leffler struct mwl_hal_hwstats {
234cf4c5a53SSam Leffler uint32_t TxRetrySuccesses; /* tx success w/ 1 retry */
235cf4c5a53SSam Leffler uint32_t TxMultipleRetrySuccesses;/* tx success w/ >1 retry */
236cf4c5a53SSam Leffler uint32_t TxFailures; /* tx fail due to no ACK */
237cf4c5a53SSam Leffler uint32_t RTSSuccesses; /* CTS rx'd for RTS */
238cf4c5a53SSam Leffler uint32_t RTSFailures; /* CTS not rx'd for RTS */
239cf4c5a53SSam Leffler uint32_t AckFailures; /* same as TxFailures */
240cf4c5a53SSam Leffler uint32_t RxDuplicateFrames; /* rx discard for dup seqno */
241cf4c5a53SSam Leffler uint32_t FCSErrorCount; /* rx discard for bad FCS */
242cf4c5a53SSam Leffler uint32_t TxWatchDogTimeouts; /* MAC tx hang (f/w recovery) */
243cf4c5a53SSam Leffler uint32_t RxOverflows; /* no f/w buffer for rx data */
244cf4c5a53SSam Leffler uint32_t RxFragErrors; /* !rx fail due to defrag */
245cf4c5a53SSam Leffler uint32_t RxMemErrors; /* out of mem or desc corrupted
246cf4c5a53SSam Leffler in some way */
247cf4c5a53SSam Leffler uint32_t RxPointerErrors; /* MAC internal ptr problem */
248cf4c5a53SSam Leffler uint32_t TxUnderflows; /* !tx underflow on dma */
249cf4c5a53SSam Leffler uint32_t TxDone; /* MAC tx ops completed
250cf4c5a53SSam Leffler (possibly w/ error) */
251cf4c5a53SSam Leffler uint32_t TxDoneBufTryPut; /* ! */
252cf4c5a53SSam Leffler uint32_t TxDoneBufPut; /* same as TxDone */
253cf4c5a53SSam Leffler uint32_t Wait4TxBuf; /* !no f/w buf avail when
254cf4c5a53SSam Leffler supplied a tx descriptor */
255cf4c5a53SSam Leffler uint32_t TxAttempts; /* tx descriptors processed */
256cf4c5a53SSam Leffler uint32_t TxSuccesses; /* tx attempts successful */
257cf4c5a53SSam Leffler uint32_t TxFragments; /* tx with fragmentation */
258cf4c5a53SSam Leffler uint32_t TxMulticasts; /* tx multicast frames */
259cf4c5a53SSam Leffler uint32_t RxNonCtlPkts; /* rx non-control frames */
260cf4c5a53SSam Leffler uint32_t RxMulticasts; /* rx multicast frames */
261cf4c5a53SSam Leffler uint32_t RxUndecryptableFrames; /* rx failed due to crypto */
262cf4c5a53SSam Leffler uint32_t RxICVErrors; /* rx failed due to ICV check */
263cf4c5a53SSam Leffler uint32_t RxExcludedFrames; /* rx discarded, e.g. bssid */
264cf4c5a53SSam Leffler };
265cf4c5a53SSam Leffler int mwl_hal_gethwstats(struct mwl_hal *mh, struct mwl_hal_hwstats *);
266cf4c5a53SSam Leffler
267cf4c5a53SSam Leffler /*
268cf4c5a53SSam Leffler * Set HT Guard Interval.
269cf4c5a53SSam Leffler *
270cf4c5a53SSam Leffler * GIType = 0: enable long and short GI
271cf4c5a53SSam Leffler * GIType = 1: enable short GI
272cf4c5a53SSam Leffler * GIType = 2: enable long GI
273cf4c5a53SSam Leffler */
274cf4c5a53SSam Leffler int mwl_hal_sethtgi(struct mwl_hal_vap *, int GIType);
275cf4c5a53SSam Leffler
276cf4c5a53SSam Leffler /*
277cf4c5a53SSam Leffler * Set Radio Configuration.
278cf4c5a53SSam Leffler *
279cf4c5a53SSam Leffler * onoff != 0 turns radio on; otherwise off.
280cf4c5a53SSam Leffler * if radio is enabled, the preamble is set too.
281cf4c5a53SSam Leffler */
282cf4c5a53SSam Leffler typedef enum {
283cf4c5a53SSam Leffler WL_LONG_PREAMBLE = 1,
284cf4c5a53SSam Leffler WL_SHORT_PREAMBLE = 3,
285cf4c5a53SSam Leffler WL_AUTO_PREAMBLE = 5,
286cf4c5a53SSam Leffler } MWL_HAL_PREAMBLE;
287cf4c5a53SSam Leffler int mwl_hal_setradio(struct mwl_hal *mh, int onoff, MWL_HAL_PREAMBLE preamble);
288cf4c5a53SSam Leffler
289cf4c5a53SSam Leffler /*
290cf4c5a53SSam Leffler * Set Antenna Configuration (legacy operation).
291cf4c5a53SSam Leffler *
2926bccea7cSRebecca Cran * The RX antenna can be selected using the bitmask
293cf4c5a53SSam Leffler * ant (bit 0 = antenna 1, bit 1 = antenna 2, etc.)
294cf4c5a53SSam Leffler * (diversity?XXX)
295cf4c5a53SSam Leffler */
296cf4c5a53SSam Leffler typedef enum {
297cf4c5a53SSam Leffler WL_ANTENNATYPE_RX = 1,
298cf4c5a53SSam Leffler WL_ANTENNATYPE_TX = 2,
299cf4c5a53SSam Leffler } MWL_HAL_ANTENNA;
300cf4c5a53SSam Leffler int mwl_hal_setantenna(struct mwl_hal *mh, MWL_HAL_ANTENNA dirSet, int ant);
301cf4c5a53SSam Leffler
302cf4c5a53SSam Leffler /*
303cf4c5a53SSam Leffler * Set the threshold for using RTS on TX.
304cf4c5a53SSam Leffler */
305cf4c5a53SSam Leffler int mwl_hal_setrtsthreshold(struct mwl_hal_vap *, int threshold);
306cf4c5a53SSam Leffler
307cf4c5a53SSam Leffler /*
308cf4c5a53SSam Leffler * Set the adapter to operate in infrastructure mode.
309cf4c5a53SSam Leffler */
310cf4c5a53SSam Leffler int mwl_hal_setinframode(struct mwl_hal_vap *);
311cf4c5a53SSam Leffler
312cf4c5a53SSam Leffler /*
313cf4c5a53SSam Leffler * Set Radar Detection Configuration.
314cf4c5a53SSam Leffler */
315cf4c5a53SSam Leffler typedef enum {
316cf4c5a53SSam Leffler DR_DFS_DISABLE = 0,
317cf4c5a53SSam Leffler DR_CHK_CHANNEL_AVAILABLE_START = 1,
318cf4c5a53SSam Leffler DR_CHK_CHANNEL_AVAILABLE_STOP = 2,
319cf4c5a53SSam Leffler DR_IN_SERVICE_MONITOR_START = 3
320cf4c5a53SSam Leffler } MWL_HAL_RADAR;
321cf4c5a53SSam Leffler int mwl_hal_setradardetection(struct mwl_hal *mh, MWL_HAL_RADAR action);
322cf4c5a53SSam Leffler /*
323cf4c5a53SSam Leffler * Set the region code that selects the radar bin'ing agorithm.
324cf4c5a53SSam Leffler */
325cf4c5a53SSam Leffler int mwl_hal_setregioncode(struct mwl_hal *mh, int regionCode);
326cf4c5a53SSam Leffler
327cf4c5a53SSam Leffler /*
328cf4c5a53SSam Leffler * Initiate an 802.11h-based channel switch. The CSA ie
329cf4c5a53SSam Leffler * is included in the next beacon(s) using the specified
330cf4c5a53SSam Leffler * information and the firmware counts down until switch
331cf4c5a53SSam Leffler * time after which it notifies the driver by delivering
332cf4c5a53SSam Leffler * an interrupt with MACREG_A2HRIC_BIT_CHAN_SWITCH set in
333cf4c5a53SSam Leffler * the cause register.
334cf4c5a53SSam Leffler */
335cf4c5a53SSam Leffler int mwl_hal_setchannelswitchie(struct mwl_hal *,
336cf4c5a53SSam Leffler const MWL_HAL_CHANNEL *nextchan, uint32_t mode, uint32_t count);
337cf4c5a53SSam Leffler
338cf4c5a53SSam Leffler /*
339cf4c5a53SSam Leffler * Set regdomain code (IEEE SKU).
340cf4c5a53SSam Leffler */
341cf4c5a53SSam Leffler enum {
342cf4c5a53SSam Leffler DOMAIN_CODE_FCC = 0x10, /* USA */
343cf4c5a53SSam Leffler DOMAIN_CODE_IC = 0x20, /* Canda */
344cf4c5a53SSam Leffler DOMAIN_CODE_ETSI = 0x30, /* Europe */
345cf4c5a53SSam Leffler DOMAIN_CODE_SPAIN = 0x31, /* Spain */
346cf4c5a53SSam Leffler DOMAIN_CODE_FRANCE = 0x32, /* France */
347cf4c5a53SSam Leffler DOMAIN_CODE_ETSI_131 = 0x130,/* ETSI w/ 1.3.1 radar type */
348cf4c5a53SSam Leffler DOMAIN_CODE_MKK = 0x40, /* Japan */
349cf4c5a53SSam Leffler DOMAIN_CODE_MKK2 = 0x41, /* Japan w/ 10MHz chan spacing */
350cf4c5a53SSam Leffler DOMAIN_CODE_DGT = 0x80, /* Taiwan */
351cf4c5a53SSam Leffler DOMAIN_CODE_AUS = 0x81, /* Australia */
352cf4c5a53SSam Leffler };
353cf4c5a53SSam Leffler
354cf4c5a53SSam Leffler /*
355cf4c5a53SSam Leffler * Transmit rate control. Rate codes with bit 0x80 set are
356cf4c5a53SSam Leffler * interpreted as MCS codes (this limits us to 0-127). The
357cf4c5a53SSam Leffler * transmit rate can be set to a single fixed rate or can
358cf4c5a53SSam Leffler * be configured to start at an initial rate and drop based
359cf4c5a53SSam Leffler * on retry counts.
360cf4c5a53SSam Leffler */
361cf4c5a53SSam Leffler typedef enum {
362cf4c5a53SSam Leffler RATE_AUTO = 0, /* rate selected by firmware */
363cf4c5a53SSam Leffler RATE_FIXED = 2, /* rate fixed */
364cf4c5a53SSam Leffler RATE_FIXED_DROP = 1, /* rate starts fixed but may drop */
365cf4c5a53SSam Leffler } MWL_HAL_TXRATE_HANDLING;
366cf4c5a53SSam Leffler
367cf4c5a53SSam Leffler typedef struct {
368cf4c5a53SSam Leffler uint8_t McastRate; /* rate for multicast frames */
369cf4c5a53SSam Leffler #define RATE_MCS 0x80 /* rate is an MCS index */
370cf4c5a53SSam Leffler uint8_t MgtRate; /* rate for management frames */
371cf4c5a53SSam Leffler struct {
372cf4c5a53SSam Leffler uint8_t TryCount; /* try this many times */
373cf4c5a53SSam Leffler uint8_t Rate; /* use this tx rate */
374cf4c5a53SSam Leffler } RateSeries[4]; /* rate series */
375cf4c5a53SSam Leffler } MWL_HAL_TXRATE;
376cf4c5a53SSam Leffler
377cf4c5a53SSam Leffler int mwl_hal_settxrate(struct mwl_hal_vap *,
378cf4c5a53SSam Leffler MWL_HAL_TXRATE_HANDLING handling, const MWL_HAL_TXRATE *rate);
379cf4c5a53SSam Leffler /* NB: hack for setting rates while scanning */
380cf4c5a53SSam Leffler int mwl_hal_settxrate_auto(struct mwl_hal *, const MWL_HAL_TXRATE *rate);
381cf4c5a53SSam Leffler
382cf4c5a53SSam Leffler /*
383cf4c5a53SSam Leffler * Set the Slot Time Configuration.
384cf4c5a53SSam Leffler * NB: usecs must either be 9 or 20 for now.
385cf4c5a53SSam Leffler */
386cf4c5a53SSam Leffler int mwl_hal_setslottime(struct mwl_hal *mh, int usecs);
387cf4c5a53SSam Leffler
388cf4c5a53SSam Leffler /*
389cf4c5a53SSam Leffler * Adjust current transmit power settings according to powerLevel.
390cf4c5a53SSam Leffler * This translates to low/medium/high use of the current tx power rate tables.
391cf4c5a53SSam Leffler */
392cf4c5a53SSam Leffler int mwl_hal_adjusttxpower(struct mwl_hal *, uint32_t powerLevel);
393cf4c5a53SSam Leffler /*
394cf4c5a53SSam Leffler * Set the transmit power for the specified channel; the power
395cf4c5a53SSam Leffler * is taken from the calibration data and capped according to
396cf4c5a53SSam Leffler * the specified max tx power (in dBm).
397cf4c5a53SSam Leffler */
398cf4c5a53SSam Leffler int mwl_hal_settxpower(struct mwl_hal *, const MWL_HAL_CHANNEL *,
399cf4c5a53SSam Leffler uint8_t maxtxpow);
400cf4c5a53SSam Leffler
401cf4c5a53SSam Leffler /*
402cf4c5a53SSam Leffler * Set the Multicast Address Filter.
403cf4c5a53SSam Leffler * A packed array addresses is specified.
404cf4c5a53SSam Leffler */
405cf4c5a53SSam Leffler #define MWL_HAL_MCAST_MAX 32
406cf4c5a53SSam Leffler int mwl_hal_setmcast(struct mwl_hal *mh, int nmc, const uint8_t macs[]);
407cf4c5a53SSam Leffler
408cf4c5a53SSam Leffler /*
409cf4c5a53SSam Leffler * Crypto Configuration.
410cf4c5a53SSam Leffler */
411cf4c5a53SSam Leffler typedef struct {
412cf4c5a53SSam Leffler uint16_t pad;
413cf4c5a53SSam Leffler uint16_t keyTypeId;
414cf4c5a53SSam Leffler #define KEY_TYPE_ID_WEP 0
415cf4c5a53SSam Leffler #define KEY_TYPE_ID_TKIP 1
416cf4c5a53SSam Leffler #define KEY_TYPE_ID_AES 2 /* AES-CCMP */
417cf4c5a53SSam Leffler uint32_t keyFlags;
418cf4c5a53SSam Leffler #define KEY_FLAG_INUSE 0x00000001 /* indicate key is in use */
419cf4c5a53SSam Leffler #define KEY_FLAG_RXGROUPKEY 0x00000002 /* Group key for RX only */
420cf4c5a53SSam Leffler #define KEY_FLAG_TXGROUPKEY 0x00000004 /* Group key for TX */
421cf4c5a53SSam Leffler #define KEY_FLAG_PAIRWISE 0x00000008 /* pairwise */
422cf4c5a53SSam Leffler #define KEY_FLAG_RXONLY 0x00000010 /* only used for RX */
423cf4c5a53SSam Leffler #define KEY_FLAG_AUTHENTICATOR 0x00000020 /* Key is for Authenticator */
424cf4c5a53SSam Leffler #define KEY_FLAG_TSC_VALID 0x00000040 /* Sequence counters valid */
425cf4c5a53SSam Leffler #define KEY_FLAG_WEP_TXKEY 0x01000000 /* Tx key for WEP */
426cf4c5a53SSam Leffler #define KEY_FLAG_MICKEY_VALID 0x02000000 /* Tx/Rx MIC keys are valid */
427cf4c5a53SSam Leffler uint32_t keyIndex; /* for WEP only; actual key index */
428cf4c5a53SSam Leffler uint16_t keyLen; /* key size in bytes */
429cf4c5a53SSam Leffler union { /* key material, keyLen gives size */
430cf4c5a53SSam Leffler uint8_t wep[16]; /* enough for 128 bits */
431cf4c5a53SSam Leffler uint8_t aes[16];
432cf4c5a53SSam Leffler struct {
433cf4c5a53SSam Leffler /* NB: group or pairwise key is determined by keyFlags */
434cf4c5a53SSam Leffler uint8_t keyMaterial[16];
435cf4c5a53SSam Leffler uint8_t txMic[8];
436cf4c5a53SSam Leffler uint8_t rxMic[8];
437cf4c5a53SSam Leffler struct {
438cf4c5a53SSam Leffler uint16_t low;
439cf4c5a53SSam Leffler uint32_t high;
440cf4c5a53SSam Leffler } rsc;
441cf4c5a53SSam Leffler struct {
442cf4c5a53SSam Leffler uint16_t low;
443cf4c5a53SSam Leffler uint32_t high;
444cf4c5a53SSam Leffler } tsc;
445cf4c5a53SSam Leffler } __packed tkip;
446cf4c5a53SSam Leffler }__packed key;
447cf4c5a53SSam Leffler } __packed MWL_HAL_KEYVAL;
448cf4c5a53SSam Leffler
449cf4c5a53SSam Leffler /*
450cf4c5a53SSam Leffler * Plumb a unicast/group key. The mac address identifies
451cf4c5a53SSam Leffler * the station, use the broadcast address for group keys.
452cf4c5a53SSam Leffler */
453cf4c5a53SSam Leffler int mwl_hal_keyset(struct mwl_hal_vap *, const MWL_HAL_KEYVAL *kv,
454cf4c5a53SSam Leffler const uint8_t mac[6]);
455cf4c5a53SSam Leffler
456cf4c5a53SSam Leffler /*
457cf4c5a53SSam Leffler * Plumb a unicast/group key. The mac address identifies
458cf4c5a53SSam Leffler * the station, use the broadcast address for group keys.
459cf4c5a53SSam Leffler */
460cf4c5a53SSam Leffler int mwl_hal_keyreset(struct mwl_hal_vap *, const MWL_HAL_KEYVAL *kv,
461cf4c5a53SSam Leffler const uint8_t mac[6]);
462cf4c5a53SSam Leffler
463cf4c5a53SSam Leffler /*
464cf4c5a53SSam Leffler * Set the MAC address.
465cf4c5a53SSam Leffler */
466cf4c5a53SSam Leffler int mwl_hal_setmac(struct mwl_hal_vap *, const uint8_t addr[6]);
467cf4c5a53SSam Leffler
468cf4c5a53SSam Leffler /*
469cf4c5a53SSam Leffler * Set the beacon frame contents. The firmware will modify the
470cf4c5a53SSam Leffler * frame only to add CSA and WME ie's and to fill in dynamic fields
471cf4c5a53SSam Leffler * such as the sequence #..
472cf4c5a53SSam Leffler */
473cf4c5a53SSam Leffler int mwl_hal_setbeacon(struct mwl_hal_vap *, const void *, size_t);
474cf4c5a53SSam Leffler
475cf4c5a53SSam Leffler /*
476cf4c5a53SSam Leffler * Handle power save operation for AP operation when offloaded to
477cf4c5a53SSam Leffler * the host (SET_HW_SPEC_HOST_POWERSAVE). mwl_hal_setbss_powersave
478cf4c5a53SSam Leffler * informs the firmware whether 1+ associated stations are in power
479cf4c5a53SSam Leffler * save mode (it will then buffer mcast traffic). mwl_hal_setsta_powersave
480cf4c5a53SSam Leffler * specifies a change in power save state for an associated station.
481cf4c5a53SSam Leffler */
482cf4c5a53SSam Leffler int mwl_hal_setpowersave_bss(struct mwl_hal_vap *, uint8_t nsta);
483cf4c5a53SSam Leffler int mwl_hal_setpowersave_sta(struct mwl_hal_vap *, uint16_t aid, int ena);
484cf4c5a53SSam Leffler
485cf4c5a53SSam Leffler /*
486cf4c5a53SSam Leffler * Set Association Configuration for station operation.
487cf4c5a53SSam Leffler */
488cf4c5a53SSam Leffler int mwl_hal_setassocid(struct mwl_hal_vap *, const uint8_t bssId[6],
489cf4c5a53SSam Leffler uint16_t assocId);
490cf4c5a53SSam Leffler
491cf4c5a53SSam Leffler /*
492cf4c5a53SSam Leffler * Set the current channel.
493cf4c5a53SSam Leffler */
494cf4c5a53SSam Leffler int mwl_hal_setchannel(struct mwl_hal *mh, const MWL_HAL_CHANNEL *c);
495cf4c5a53SSam Leffler
496cf4c5a53SSam Leffler /*
497cf4c5a53SSam Leffler * A-MPDU Block Ack (BA) stream support. There are several
498cf4c5a53SSam Leffler * streams that the driver must multiplex. Once assigned
499cf4c5a53SSam Leffler * to a station the driver queues frames to a corresponding
500cf4c5a53SSam Leffler * transmit queue and the firmware handles all the work.
501cf4c5a53SSam Leffler *
502cf4c5a53SSam Leffler * XXX no way to find out how many streams are supported
503cf4c5a53SSam Leffler */
504cf4c5a53SSam Leffler typedef struct {
505cf4c5a53SSam Leffler void *data[2]; /* opaque data */
506cf4c5a53SSam Leffler int txq;
507cf4c5a53SSam Leffler } MWL_HAL_BASTREAM;
508cf4c5a53SSam Leffler
5097850fa71SSam Leffler const MWL_HAL_BASTREAM *mwl_hal_bastream_alloc(struct mwl_hal_vap *,
5107850fa71SSam Leffler int ba_type, const uint8_t Macaddr[6], uint8_t Tid,
511cf4c5a53SSam Leffler uint8_t ParamInfo, void *, void *);
512cf4c5a53SSam Leffler const MWL_HAL_BASTREAM *mwl_hal_bastream_lookup(struct mwl_hal *mh, int s);
5137850fa71SSam Leffler int mwl_hal_bastream_create(struct mwl_hal_vap *, const MWL_HAL_BASTREAM *,
514cf4c5a53SSam Leffler int BarThrs, int WindowSize, uint16_t seqno);
515cf4c5a53SSam Leffler int mwl_hal_bastream_destroy(struct mwl_hal *mh, const MWL_HAL_BASTREAM *);
516cf4c5a53SSam Leffler int mwl_hal_getwatchdogbitmap(struct mwl_hal *mh, uint8_t bitmap[1]);
5177850fa71SSam Leffler int mwl_hal_bastream_get_seqno(struct mwl_hal *mh, const MWL_HAL_BASTREAM *,
5187850fa71SSam Leffler const uint8_t Macaddr[6], uint16_t *pseqno);
519cf4c5a53SSam Leffler /* for sysctl hookup for debugging */
520cf4c5a53SSam Leffler void mwl_hal_setbastreams(struct mwl_hal *mh, int mask);
521cf4c5a53SSam Leffler int mwl_hal_getbastreams(struct mwl_hal *mh);
522cf4c5a53SSam Leffler
523cf4c5a53SSam Leffler /*
5247850fa71SSam Leffler * Set/get A-MPDU aggregation parameters.
5257850fa71SSam Leffler */
5267850fa71SSam Leffler int mwl_hal_setaggampduratemode(struct mwl_hal *, int mode, int thresh);
5277850fa71SSam Leffler int mwl_hal_getaggampduratemode(struct mwl_hal *, int *mode, int *thresh);
5287850fa71SSam Leffler
5297850fa71SSam Leffler /*
530cf4c5a53SSam Leffler * Inform the firmware of a new association station.
531cf4c5a53SSam Leffler * The address is the MAC address of the peer station.
532cf4c5a53SSam Leffler * The AID is supplied sans the 0xc000 bits. The station
533cf4c5a53SSam Leffler * ID is defined by the caller. The peer information must
534cf4c5a53SSam Leffler * be supplied.
535cf4c5a53SSam Leffler *
536cf4c5a53SSam Leffler * NB: All values are in host byte order; any byte swapping
537cf4c5a53SSam Leffler * is handled by the hal.
538cf4c5a53SSam Leffler */
539cf4c5a53SSam Leffler typedef struct {
540cf4c5a53SSam Leffler uint32_t LegacyRateBitMap;
541cf4c5a53SSam Leffler uint32_t HTRateBitMap;
542cf4c5a53SSam Leffler uint16_t CapInfo;
543cf4c5a53SSam Leffler uint16_t HTCapabilitiesInfo;
544cf4c5a53SSam Leffler uint8_t MacHTParamInfo;
545cf4c5a53SSam Leffler uint8_t Rev;
546cf4c5a53SSam Leffler struct {
547cf4c5a53SSam Leffler uint8_t ControlChan;
548cf4c5a53SSam Leffler uint8_t AddChan;
549cf4c5a53SSam Leffler uint8_t OpMode;
550cf4c5a53SSam Leffler uint8_t stbc;
551cf4c5a53SSam Leffler } __packed AddHtInfo;
552cf4c5a53SSam Leffler } __packed MWL_HAL_PEERINFO;
553cf4c5a53SSam Leffler int mwl_hal_newstation(struct mwl_hal_vap *, const uint8_t addr[6],
554cf4c5a53SSam Leffler uint16_t aid, uint16_t sid, const MWL_HAL_PEERINFO *,
555cf4c5a53SSam Leffler int isQosSta, int wmeInfo);
556cf4c5a53SSam Leffler int mwl_hal_delstation(struct mwl_hal_vap *, const uint8_t addr[6]);
557cf4c5a53SSam Leffler
558cf4c5a53SSam Leffler /*
559cf4c5a53SSam Leffler * Prod the firmware to age packets on station power
560cf4c5a53SSam Leffler * save queues and reap frames on the tx aggregation q's.
561cf4c5a53SSam Leffler */
562cf4c5a53SSam Leffler int mwl_hal_setkeepalive(struct mwl_hal *mh);
563cf4c5a53SSam Leffler
564cf4c5a53SSam Leffler typedef enum {
565cf4c5a53SSam Leffler AP_MODE_B_ONLY = 1,
566cf4c5a53SSam Leffler AP_MODE_G_ONLY = 2,
567cf4c5a53SSam Leffler AP_MODE_MIXED = 3,
568cf4c5a53SSam Leffler AP_MODE_N_ONLY = 4,
569cf4c5a53SSam Leffler AP_MODE_BandN = 5,
570cf4c5a53SSam Leffler AP_MODE_GandN = 6,
571cf4c5a53SSam Leffler AP_MODE_BandGandN = 7,
572cf4c5a53SSam Leffler AP_MODE_A_ONLY = 8,
573cf4c5a53SSam Leffler AP_MODE_AandG = 10,
574cf4c5a53SSam Leffler AP_MODE_AandN = 12,
575cf4c5a53SSam Leffler } MWL_HAL_APMODE;
576cf4c5a53SSam Leffler int mwl_hal_setapmode(struct mwl_hal_vap *, MWL_HAL_APMODE);
577cf4c5a53SSam Leffler
578cf4c5a53SSam Leffler /*
579cf4c5a53SSam Leffler * Enable/disable firmware operation. mwl_hal_start is
580cf4c5a53SSam Leffler * also used to sync state updates, e.g. beacon frame
581cf4c5a53SSam Leffler * reconstruction after content changes.
582cf4c5a53SSam Leffler */
583cf4c5a53SSam Leffler int mwl_hal_stop(struct mwl_hal_vap *);
584cf4c5a53SSam Leffler int mwl_hal_start(struct mwl_hal_vap *);
585cf4c5a53SSam Leffler
586cf4c5a53SSam Leffler /*
5877850fa71SSam Leffler * Add/Remove station from Power Save TIM handling.
5887850fa71SSam Leffler *
5897850fa71SSam Leffler * If set is non-zero the AID is enabled, if zero it is removed.
5907850fa71SSam Leffler */
5917850fa71SSam Leffler int mwl_hal_updatetim(struct mwl_hal_vap *, uint16_t aid, int set);
5927850fa71SSam Leffler
5937850fa71SSam Leffler /*
594cf4c5a53SSam Leffler * Enable/disable 11g protection use. This call specifies
595cf4c5a53SSam Leffler * the ERP information element flags to use.
596cf4c5a53SSam Leffler */
597cf4c5a53SSam Leffler int mwl_hal_setgprot(struct mwl_hal *, int);
598cf4c5a53SSam Leffler
599cf4c5a53SSam Leffler /*
600cf4c5a53SSam Leffler * Enable/disable WMM support.
601cf4c5a53SSam Leffler */
602cf4c5a53SSam Leffler int mwl_hal_setwmm(struct mwl_hal *mh, int onoff);
603cf4c5a53SSam Leffler
604cf4c5a53SSam Leffler /*
605cf4c5a53SSam Leffler * Configure WMM EDCA parameters for the specified h/w ring.
606cf4c5a53SSam Leffler */
607cf4c5a53SSam Leffler int mwl_hal_setedcaparams(struct mwl_hal *mh, uint8_t qnum,
608cf4c5a53SSam Leffler uint32_t CWmin, uint32_t CWmax, uint8_t AIFSN, uint16_t TXOPLimit);
609cf4c5a53SSam Leffler
610cf4c5a53SSam Leffler /*
611cf4c5a53SSam Leffler * Configure rate adaptation for indooor/outdoor operation.
612cf4c5a53SSam Leffler * XXX wtf?
613cf4c5a53SSam Leffler */
614cf4c5a53SSam Leffler int mwl_hal_setrateadaptmode(struct mwl_hal *mh, uint16_t mode);
615cf4c5a53SSam Leffler
616cf4c5a53SSam Leffler typedef enum {
617cf4c5a53SSam Leffler CSMODE_CONSERVATIVE = 0,
618cf4c5a53SSam Leffler CSMODE_AGGRESSIVE = 1,
619cf4c5a53SSam Leffler CSMODE_AUTO_ENA = 2,
620cf4c5a53SSam Leffler CSMODE_AUTO_DIS = 3,
621cf4c5a53SSam Leffler } MWL_HAL_CSMODE;
622cf4c5a53SSam Leffler int mwl_hal_setcsmode(struct mwl_hal *mh, MWL_HAL_CSMODE csmode);
623cf4c5a53SSam Leffler
624cf4c5a53SSam Leffler /*
625cf4c5a53SSam Leffler * Configure 11n protection on/off.
626cf4c5a53SSam Leffler */
627cf4c5a53SSam Leffler typedef enum {
628cf4c5a53SSam Leffler HTPROTECT_NONE = 0, /* disable */
629cf4c5a53SSam Leffler HTPROTECT_OPT = 1, /* optional */
630cf4c5a53SSam Leffler HTPROTECT_HT20 = 2, /* protect only HT20 */
631cf4c5a53SSam Leffler HTPROTECT_HT2040 = 3, /* protect HT20/40 */
632cf4c5a53SSam Leffler HTPROTECT_AUTO = 4, /* automatic */
633cf4c5a53SSam Leffler } MWL_HAL_HTPROTECT;
634cf4c5a53SSam Leffler int mwl_hal_setnprot(struct mwl_hal_vap *, MWL_HAL_HTPROTECT mode);
635cf4c5a53SSam Leffler /*
636cf4c5a53SSam Leffler * Configure 11n protection mechanism for when protection is enabled.
637cf4c5a53SSam Leffler */
638cf4c5a53SSam Leffler int mwl_hal_setnprotmode(struct mwl_hal_vap *, uint8_t mode);
639cf4c5a53SSam Leffler
640cf4c5a53SSam Leffler /*
641cf4c5a53SSam Leffler * Enable/disable Marvell "turbo mode"".
642cf4c5a53SSam Leffler */
643cf4c5a53SSam Leffler int mwl_hal_setoptimizationlevel(struct mwl_hal *mh, int onoff);
644cf4c5a53SSam Leffler
645cf4c5a53SSam Leffler /*
646cf4c5a53SSam Leffler * Set MIMO Power Save handling for a station; the enable and mode
647cf4c5a53SSam Leffler * values come directly from the Action frame.
648cf4c5a53SSam Leffler */
649cf4c5a53SSam Leffler int mwl_hal_setmimops(struct mwl_hal *mh, const uint8_t addr[6],
650cf4c5a53SSam Leffler uint8_t enable, uint8_t mode);
651cf4c5a53SSam Leffler
652cf4c5a53SSam Leffler /*
653cf4c5a53SSam Leffler * Retrieve the region/country code from the EEPROM.
654cf4c5a53SSam Leffler */
655cf4c5a53SSam Leffler int mwl_hal_getregioncode(struct mwl_hal *mh, uint8_t *countryCode);
656cf4c5a53SSam Leffler int mwl_hal_GetBeacon(struct mwl_hal *mh, uint8_t *pBcn, uint16_t *pLen);
657cf4c5a53SSam Leffler int mwl_hal_SetRifs(struct mwl_hal *mh, uint8_t QNum);
658cf4c5a53SSam Leffler
659cf4c5a53SSam Leffler /*
660cf4c5a53SSam Leffler * Set/get promiscuous mode.
661cf4c5a53SSam Leffler */
662cf4c5a53SSam Leffler int mwl_hal_setpromisc(struct mwl_hal *, int ena);
663cf4c5a53SSam Leffler int mwl_hal_getpromisc(struct mwl_hal *);
664cf4c5a53SSam Leffler
665cf4c5a53SSam Leffler /*
6667850fa71SSam Leffler * Enable/disable CF-End use.
6677850fa71SSam Leffler */
6687850fa71SSam Leffler int mwl_hal_setcfend(struct mwl_hal *, int ena);
6697850fa71SSam Leffler
6707850fa71SSam Leffler /*
6717850fa71SSam Leffler * Enable/disable sta-mode DWDS use/operation.
6727850fa71SSam Leffler */
6737850fa71SSam Leffler int mwl_hal_setdwds(struct mwl_hal *, int ena);
6747850fa71SSam Leffler
6757850fa71SSam Leffler /*
676cf4c5a53SSam Leffler * Diagnostic interface. This is an open-ended interface that
677cf4c5a53SSam Leffler * is opaque to applications. Diagnostic programs use this to
678cf4c5a53SSam Leffler * retrieve internal data structures, etc. There is no guarantee
679cf4c5a53SSam Leffler * that calling conventions for calls other than MWL_DIAG_REVS
680cf4c5a53SSam Leffler * are stable between HAL releases; a diagnostic application must
681cf4c5a53SSam Leffler * use the HAL revision information to deal with ABI/API differences.
682cf4c5a53SSam Leffler */
683cf4c5a53SSam Leffler int mwl_hal_getdiagstate(struct mwl_hal *mh, int request,
684cf4c5a53SSam Leffler const void *args, uint32_t argsize,
685cf4c5a53SSam Leffler void **result, uint32_t *resultsize);
686cf4c5a53SSam Leffler
687cf4c5a53SSam Leffler int mwl_hal_fwload(struct mwl_hal *mh, void *fwargs);
688cf4c5a53SSam Leffler #endif /* _MWL_HAL_H_ */
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