Lines Matching +full:rx +full:- +full:enable
1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2004 Atheros Communications, Inc.
24 * Processor for IEEE 802.11a 5-GHz Wireless LANs.
37 #define AR_RXDP 0x000c /* RX queue descriptor ptr register */
41 #define AR_IER 0x0024 /* Interrupt global enable register */
45 #define AR_RXCFG 0x0034 /* RX configuration register */
48 #define AR_RXNOFRM 0x0048 /* RX no frame timeout register */
50 #define AR_RPGTO 0x0050 /* RX frame gap timeout register */
51 #define AR_RFCNT 0x0054 /* RX frame count limit register */
72 #define AR_SLOT_TIME 0x8010 /* Length of a back-off */
98 #define AR_BACKOFF 0x8088 /* Back-off status */
108 #define AR_CR_TXE0 0x00000001 /* TX queue 0 enable */
109 #define AR_CR_TXE1 0x00000002 /* TX queue 1 enable */
110 #define AR_CR_RXE 0x00000004 /* RX enable */
113 #define AR_CR_RXD 0x00000020 /* RX disable */
120 #define AR_CFG_SWRD 0x00000004 /* BE for RX desc */
121 #define AR_CFG_SWRB 0x00000008 /* BE for RX data */
127 #define AR_CFG_TXFSTRT 0x00010000 /* re-enable TX DMA */
131 #define AR_ISR_RXOK_INT 0x00000001 /* RX frame OK */
132 #define AR_ISR_RXDESC_INT 0x00000002 /* RX intr request */
133 #define AR_ISR_RXERR_INT 0x00000004 /* RX error */
135 #define AR_ISR_RXEOL_INT 0x00000010 /* RX desc empty */
136 #define AR_ISR_RXORN_INT 0x00000020 /* RX fifo overrun */
145 #define AR_ISR_RXPHY_INT 0x00004000 /* PHY RX error */
159 #define AR_IMR_RXOK_INT 0x00000001 /* RX frame OK */
160 #define AR_IMR_RXDESC_INT 0x00000002 /* RX intr request */
161 #define AR_IMR_RXERR_INT 0x00000004 /* RX error */
163 #define AR_IMR_RXEOL_INT 0x00000010 /* RX desc empty */
164 #define AR_IMR_RXORN_INT 0x00000020 /* RX fifo overrun */
173 #define AR_IMR_RXPHY_INT 0x00004000 /* PHY RX error */
184 #define AR_IER_DISABLE 0x00000000 /* pseudo-flag */
185 #define AR_IER_ENABLE 0x00000001 /* global interrupt enable */
186 #define AR_IER_BITS "\20\1ENABLE"
189 #define AR_BCR_BDMAE 0x00000002 /* beacon DMA enable */
190 #define AR_BCR_TQ1FV 0x00000004 /* use TXQ1 for non-beacon */
212 #define AR_TXCFG_TXCONT_EN 0x00000080 /* Enable continuous TX mode */
216 #define AR_RXCFG_ZLFDMA 0x00000010 /* enable zero length DMA */
233 #define AR_RFCNT_RFCL 0x0000000f /* RX frame count limit */
246 #define AR_SCR_SLE 0x00030000 /* sleep enable */
255 * However, these have been pre-shifted with AR_SCR_SLE_S. The
269 #define AR_PCICFG_EEPROMSEL 0x00000001 /* EEPROM access enable */
270 #define AR_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable */
273 #define AR_PCICFG_SL_INTEN 0x00000800 /* Enable sleep intr */
281 #define AR_GPIOCR_IN(n) (0<<((n)*2)) /* input-only */
282 #define AR_GPIOCR_OUT0(n) (1<<((n)*2)) /* output-only if GPIODO = 0 */
283 #define AR_GPIOCR_OUT1(n) (2<<((n)*2)) /* output-only if GPIODO = 1 */
287 #define AR_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */
304 #define AR_STA_ID1_PWR_SV 0x00040000 /* power save report enable */
306 #define AR_STA_ID1_NO_PSPOLL 0x00100000 /* auto PS-POLL disable */
307 #define AR_STA_ID1_PCF 0x00200000 /* PCF observation enable */
350 #define AR_BEACON_EN 0x00800000 /* beacon transmission enable */
352 #define AR_BEACON_BITS "\20\27ENABLE\30RESET_TSF"
363 #define AR_IFS1_CS_EN 0x04000000 /* carrier sense enable */
365 #define AR_RX_FILTER_UNICAST 0x00000001 /* unicast frame enable */
366 #define AR_RX_FILTER_MULTICAST 0x00000002 /* multicast frame enable */
367 #define AR_RX_FILTER_BROADCAST 0x00000004 /* broadcast frame enable */
368 #define AR_RX_FILTER_CONTROL 0x00000008 /* control frame enable */
369 #define AR_RX_FILTER_BEACON 0x00000010 /* beacon frame enable */
370 #define AR_RX_FILTER_PROMISCUOUS 0x00000020 /* promiscuous receive enable */
380 #define AR_DIAG_SW_DIS_RX 0x00000040 /* RX disable */
381 #define AR_DIAG_SW_LOOP_BACK 0x00000080 /* TX data loopback enable */
382 #define AR_DIAG_SW_CORR_FCS 0x00000100 /* corrupt FCS enable */
383 #define AR_DIAG_SW_CHAN_INFO 0x00000200 /* channel information enable */
400 #define AR_KEYTABLE_KEY0(n) (AR_KEYTABLE(n) + 0) /* key bit 0-31 */
401 #define AR_KEYTABLE_KEY1(n) (AR_KEYTABLE(n) + 4) /* key bit 32-47 */
402 #define AR_KEYTABLE_KEY2(n) (AR_KEYTABLE(n) + 8) /* key bit 48-79 */
403 #define AR_KEYTABLE_KEY3(n) (AR_KEYTABLE(n) + 12) /* key bit 80-95 */
404 #define AR_KEYTABLE_KEY4(n) (AR_KEYTABLE(n) + 16) /* key bit 96-127 */
409 #define AR_KEYTABLE_MAC0(n) (AR_KEYTABLE(n) + 24) /* MAC address 1-32 */
410 #define AR_KEYTABLE_MAC1(n) (AR_KEYTABLE(n) + 28) /* MAC address 33-47 */