Lines Matching +full:rx +full:- +full:enable
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
16 #define IGC_WUC_APME 0x00000001 /* APM Enable */
17 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
23 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
24 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
25 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
26 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
27 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
28 #define IGC_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
29 #define IGC_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
98 #define IGC_RXD_ERR_RXE 0x80 /* Rx Data Error */
128 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
129 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
130 #define IGC_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
133 /* Enable MAC address filtering */
135 /* Enable MNG packets to host memory */
145 #define IGC_RCTL_EN 0x00000002 /* enable */
147 #define IGC_RCTL_UPE 0x00000008 /* unicast promisc enable */
148 #define IGC_RCTL_MPE 0x00000010 /* multicast promisc enable */
149 #define IGC_RCTL_LPE 0x00000020 /* long packet enable */
154 #define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
159 #define IGC_RCTL_BAM 0x00008000 /* broadcast enable */
161 #define IGC_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
162 #define IGC_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
163 #define IGC_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
164 #define IGC_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
166 #define IGC_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
167 #define IGC_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
168 #define IGC_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
169 #define IGC_RCTL_VFE 0x00040000 /* vlan filter enable */
170 #define IGC_RCTL_CFIEN 0x00080000 /* canonical form enable */
212 #define IGC_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
215 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
217 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
232 #define IGC_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
233 #define IGC_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
234 #define IGC_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
279 /* 1000/H is not supported, nor spec-compliant. */
317 #define IGC_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
321 #define IGC_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
325 #define IGC_TCTL_EN 0x00000002 /* enable Tx */
329 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
333 #define IGC_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
342 #define IGC_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
343 #define IGC_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
346 /* GPY211 - I225 defines */
427 /* Uncorrectable/correctable ECC Error counts and enable bits */
450 #define IGC_ICR_RXSEQ 0x00000008 /* Rx sequence error */
451 #define IGC_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
452 #define IGC_ICR_RXO 0x00000040 /* Rx overrun */
453 #define IGC_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
454 #define IGC_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
471 #define IGC_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
472 #define IGC_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
473 #define IGC_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
474 #define IGC_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
483 #define IGC_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
505 #define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */
506 #define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */
507 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
509 #define IGC_IMS_RXO IGC_ICR_RXO /* Rx overrun */
510 #define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
521 #define IGC_EIMS_RX_QUEUE0 IGC_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
522 #define IGC_EIMS_RX_QUEUE1 IGC_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
523 #define IGC_EIMS_RX_QUEUE2 IGC_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
524 #define IGC_EIMS_RX_QUEUE3 IGC_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
534 #define IGC_ICS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */
535 #define IGC_ICS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */
538 #define IGC_EICS_RX_QUEUE0 IGC_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
539 #define IGC_EICS_RX_QUEUE1 IGC_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
540 #define IGC_EICS_RX_QUEUE2 IGC_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
541 #define IGC_EICS_RX_QUEUE3 IGC_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
561 /* Enable the counting of descriptors still to be processed. */
605 /* Loop limit on how long we wait for auto-negotiation to complete */
620 #define IGC_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
627 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
636 #define IGC_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
638 #define IGC_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
639 #define IGC_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
645 #define IGC_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
682 #define TSAUXC_EN_TT0 (1 << 0) /* Enable target time 0. */
683 #define TSAUXC_EN_TT1 (1 << 1) /* Enable target time 1. */
684 #define TSAUXC_EN_CLK0 (1 << 2) /* Enable Configurable Frequency Clock 0. */
686 #define TSAUXC_EN_CLK1 (1 << 5) /* Enable Configurable Frequency Clock 1. */
688 #define TSAUXC_EN_TS0 (1 << 8) /* Enable hardware timestamp 0. */
689 #define TSAUXC_EN_TS1 (1 << 10) /* Enable hardware timestamp 0. */
696 #define AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */
701 #define AUX1_TS_SDP_EN (1u << 5) /* Enable auxiliary time stamp trigger 1. */
735 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
744 #define IGC_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
755 #define IGC_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
787 #define IGC_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
788 #define IGC_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
792 #define IGC_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
819 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
824 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
871 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */
881 /* 1000BASE-T Control Register */
897 /* 1000BASE-T Status Register */
920 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
921 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1031 /* NVM Commands - Microwire */
1035 #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */
1038 /* NVM Commands - SPI */
1042 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1043 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
1070 /* PCI/PCI-X/PCI-EX Config space */
1096 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1129 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1140 * 1 = 50-80M
1141 * 2 = 80-110M
1142 * 3 = 110-140M
1171 * 15-5: page
1172 * 4-0: register offset
1190 /* Page 193 - Port Control Registers */
1195 /* Page 194 - KMRN Registers */
1209 #define IGC_N0_QUEUE -1
1224 /* DMA Coalescing Rx Threshold */
1230 #define IGC_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
1231 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1239 /* Rx Traffic Rate Threshold */
1241 /* Rx packet rate in current window */
1244 /* DMA Coal Rx Traffic Current Count */
1247 /* Flow ctrl Rx Threshold High val */
1253 #define IGC_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
1254 #define IGC_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */
1259 #define IGC_LTRC_EEEMS_EN 0x00000020 /* Enable EEE LTR max send */
1260 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1264 /* Minimum time for 100BASE-T where no data will be transmit following move out
1288 #define IGC_RXPBS_SIZE_I225_MASK 0x0000003F /* Rx packet buffer size */
1338 #define IGC_PROXYFC_D0 0x00000001 /* Enable offload in D0 */
1341 #define IGC_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */
1343 #define IGC_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */
1344 #define IGC_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */