Lines Matching +full:rx +full:- +full:enable
1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
54 #define VGE_RXCTL 0x06 /* RX control register */
82 #define VGE_RXHOSTERR 0x23 /* RX host error status */
87 #define VGE_RXQCSRS 0x32 /* RX queue ctl/status set */
89 #define VGE_RXQCSRC 0x36 /* RX queue ctl/status clear */
90 #define VGE_RXDESC_ADDR_LO 0x38 /* RX desc base addr (lo 32 bits) */
91 #define VGE_RXDESC_CONSIDX 0x3C /* Current RX descriptor index */
93 #define VGE_RXQTIMER 0x3F /* RX queue timer pend register */
98 #define VGE_RXDESCNUM 0x50 /* Size of RX desc ring */
105 #define VGE_RXDESC_RESIDUECNT 0x5E /* RX descriptor residue count */
119 #define VGE_SSTIMER 0x74 /* single-shot timer */
127 #define VGE_RXCFG 0x7E /* MAC RX config */
211 #define VGE_CR0_RX_ENABLE 0x04 /* turn on RX engine */
217 #define VGE_CR1_NOPOLL 0x08 /* disable RX/TX desc polling */
218 #define VGE_CR1_TIMER0_ENABLE 0x20 /* enable single shot timer */
219 #define VGE_CR1_TIMER1_ENABLE 0x40 /* enable periodic timer */
227 #define VGE_CR2_FDX_RXFLOWCTL_ENABLE 0x20 /* full duplex RX flow control */
233 #define VGE_CR3_INT_SWPEND 0x01 /* disable multi-level int bits */
235 #define VGE_CR3_INT_HOLDOFF 0x04 /* enable int hold off timer */
243 #define VGE_INTCTL_HC_RELOAD 0x02 /* enable hold timer reload */
246 #define VGE_INTCTL_RXINTSUP_DISABLE 0x20 /* disable RX int supression */
264 #define VGE_RXHOSTERR_RDSTRUCT 0x01 /* bad RX desc structure */
267 #define VGE_RXHOSTERR_FIFOERR 0x08 /* RX FIFO DMA bus error */
271 #define VGE_ISR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */
273 #define VGE_ISR_RXOK 0x00000004 /* normal RX done */
279 #define VGE_ISR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */
280 #define VGE_ISR_RXPAUSE 0x00000800 /* pause frame RX'ed */
281 #define VGE_ISR_RXOFLOW 0x00001000 /* RX FIFO overflow */
282 #define VGE_ISR_RXNODESC 0x00002000 /* ran out of RX descriptors */
283 #define VGE_ISR_RXNODESC_WARN 0x00004000 /* running out of RX descs */
293 #define VGE_ISR_RXDMA_STALL 0x01000000 /* RX DMA stall */
309 #define VGE_IMR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */
311 #define VGE_IMR_RXOK 0x00000004 /* normal RX done */
317 #define VGE_IMR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */
318 #define VGE_IMR_RXPAUSE 0x00000800 /* pause frame RX'ed */
319 #define VGE_IMR_RXOFLOW 0x00001000 /* RX FIFO overflow */
320 #define VGE_IMR_RXNODESC 0x00002000 /* ran out of RX descriptors */
321 #define VGE_IMR_RXNODESC_WARN 0x00004000 /* running out of RX descs */
331 #define VGE_IMR_RXDMA_STALL 0x01000000 /* RX DMA stall */
340 #define VGE_TXQCSR_RUN0 0x0001 /* Enable TX queue 0 */
344 #define VGE_TXQCSR_RUN1 0x0010 /* Enable TX queue 1 */
348 #define VGE_TXQCSR_RUN2 0x0100 /* Enable TX queue 2 */
352 #define VGE_TXQCSR_RUN3 0x1000 /* Enable TX queue 3 */
357 /* RX descriptor queue control/status register */
359 #define VGE_RXQCSR_RUN 0x0001 /* Enable RX queue */
364 /* RX/TX queue empty interrupt delay timer register */
378 #define VGE_CAMADDR_ENABLE 0x80 /* enable CAM read/write */
386 * - The behavior of the MAR0/MAR1 registers at offset 0x10 (the
389 * - The behavior of the interrupt holdoff timer register at offset
392 * RX interrupt supression count)
393 * - The behavior the WOL pattern programming registers at offset
400 #define VGE_CAMCTL_INTPKT_ENB 0x20 /* enable interesting packet mode */
432 #define VGE_PHYSTS_RXFLOWCAP 0x02 /* resolved RX flow control cap */
444 #define VGE_MIICMD_MOUT 0x08 /* data out pin enable */
445 #define VGE_MIICMD_MDP 0x10 /* enable direct programming mode */
448 #define VGE_MIICMD_MAUTO 0x80 /* enable autopolling */
456 #define VGE_CHIPCFG0_PACPI 0x01 /* pre-ACPI wakeup function */
458 #define VGE_CHIPCFG0_GPIO1PD 0x04 /* GPIO pin enable */
476 #define VGE_CHIPCFG2_EELOAD 0x80 /* enable EEPROM programming */
480 #define VGE_CHIPCFG3_64BIT_DAC 0x20 /* enable 64bit via DAC */
485 #define VGE_DMACFG0_BURSTLEN 0x07 /* RX/TX DMA burst (in dwords) */
497 #define VGE_DMACFG1_LATENB 0x01 /* Latency timer enable */
504 /* RX MAC config register */
508 #define VGE_RXCFG_FIFO_LOWAT 0x08 /* RX FIFO low watermark (7QW/15QW) */
509 #define VGE_RXCFG_FIFO_THR 0x30 /* RX FIFO threshold */
513 RX: rx all, no tag extraction */
516 RX: rx only tagged pkts, no
520 RX: rx all, extract tags */
523 RX: rx only tagged pkts,
537 #define VGE_TXCFG_NONBLK 0x02 /* priority TX/non-blocking mode */
538 #define VGE_TXCFG_NONBLK_THR 0x0C /* non-blocking threshold */
590 #define VGE_MIB_CNT (VGE_MIB_TX_LATECOLLS - VGE_MIB_RX_FRAMES + 1)
636 #define VGE_EECSR_DPM 0x10 /* direct program mode enable */
638 #define VGE_EECSR_EMBP 0x40 /* embedded program mode enable */
644 #define VGE_EECMD_EWEN 0x04 /* EEPROM write enable */
650 #define VGE_DIAGCTL_PHYINT_ENB 0x01 /* Enable PHY interrupts */
739 * RX descriptor has special meaning. This bit controls whether or
749 #define VGE_RDSTS_RLERR 0x00000010 /* RX length error */
751 #define VGE_RDSTS_SNTAG 0x00000040 /* RX'ed tagged SNAP pkt */
761 #define VGE_RDSTS_SHUTDOWN 0x40000000 /* shutdown during RX */