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/linux/drivers/gpu/drm/xe/
H A DMakefile210 # i915 Display compat #defines and #includes
213 -I$(srctree)/drivers/gpu/drm/i915/display/
215 # Rule to build display code shared with i915
216 $(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE
220 # Display code specific to xe
222 display/xe_display.o \
223 display/xe_display_bo.o \
224 display/xe_display_pcode.o \
225 display/xe_display_rpm.o \
226 display/xe_display_wa.o \
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.c60 * The display engine uses several different clocks to do its work. There
63 * are the core display clock (CDCLK) and RAWCLK.
65 * CDCLK clocks most of the display pipe logic, and thus its frequency
71 * to minimize power consumption for a given display configuration.
72 * Typically changes to the CDCLK frequency require all the display pipes
161 void (*get_cdclk)(struct intel_display *display,
163 void (*set_cdclk)(struct intel_display *display,
170 void intel_cdclk_get_cdclk(struct intel_display *display, in intel_cdclk_get_cdclk() argument
173 display->cdclk.funcs->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
176 static void intel_cdclk_set_cdclk(struct intel_display *display, in intel_cdclk_set_cdclk() argument
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H A Dintel_vrr.c39 struct intel_display *display = to_intel_display(connector); in intel_vrr_is_capable() local
43 if (!HAS_VRR(display)) in intel_vrr_is_capable()
114 static int intel_vrr_extra_vblank_delay(struct intel_display *display) in intel_vrr_extra_vblank_delay() argument
122 return DISPLAY_VER(display) < 13 ? 1 : 0; in intel_vrr_extra_vblank_delay()
125 static int intel_vrr_vmin_flipline_offset(struct intel_display *display) in intel_vrr_vmin_flipline_offset() argument
135 return DISPLAY_VER(display) < 13 ? 1 : 0; in intel_vrr_vmin_flipline_offset()
193 struct intel_display *display = to_intel_display(crtc_state); in is_cmrr_frac_required() local
198 if (!HAS_CMRR(display) || true) in is_cmrr_frac_required()
279 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_hw_value() local
285 if (DISPLAY_VER(display) > in intel_vrr_hw_value()
316 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_fixed_rr_hw_vmin() local
331 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_set_fixed_rr_timings() local
373 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_dc_balance_possible() local
425 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_compute_config() local
485 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_max_hw_guardband() local
498 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_max_vblank_guardband() local
517 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_compute_optimized_guardband() local
561 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_compute_guardband() local
595 struct intel_display *display = to_intel_display(crtc_state); trans_vrr_ctl() local
611 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_set_transcoder_timings() local
685 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_dcb_increment_flip_count() local
699 struct intel_display *display = to_intel_display(old_crtc_state); intel_vrr_dcb_reset() local
712 struct intel_display *display = to_intel_display(crtc_state); trans_vrr_push() local
731 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_send_push() local
750 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_check_push_sent() local
783 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_is_push_sent() local
792 intel_vrr_always_use_vrr_tg(struct intel_display * display) intel_vrr_always_use_vrr_tg() argument
805 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_hw_vmin() local
823 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_set_vrr_timings() local
837 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_enable_dc_balancing() local
888 struct intel_display *display = to_intel_display(old_crtc_state); intel_vrr_disable_dc_balancing() local
923 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_tg_enable() local
947 struct intel_display *display = to_intel_display(old_crtc_state); intel_vrr_tg_disable() local
964 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_enable() local
978 struct intel_display *display = to_intel_display(old_crtc_state); intel_vrr_disable() local
992 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_transcoder_enable() local
1005 struct intel_display *display = to_intel_display(old_crtc_state); intel_vrr_transcoder_disable() local
1016 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_psr_frame_change_enable() local
1034 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_get_dc_balance_config() local
1061 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_get_config() local
1159 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_safe_window_start() local
1187 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_dcb_vmin_vblank_start_next() local
1201 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_dcb_vmax_vblank_start_next() local
1215 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_dcb_vmin_vblank_start_final() local
1226 struct intel_display *display = to_intel_display(crtc_state); intel_vrr_dcb_vmax_vblank_start_final() local
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H A Dintel_hdcp.c17 #include <drm/display/drm_hdcp_helper.h>
48 struct intel_display *display = to_intel_display(encoder); in intel_hdcp_adjust_hdcp_line_rekeying() local
56 if (DISPLAY_VER(display) >= 30) { in intel_hdcp_adjust_hdcp_line_rekeying()
57 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); in intel_hdcp_adjust_hdcp_line_rekeying()
59 } else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) || in intel_hdcp_adjust_hdcp_line_rekeying()
60 IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) { in intel_hdcp_adjust_hdcp_line_rekeying()
61 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); in intel_hdcp_adjust_hdcp_line_rekeying()
63 } else if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) { in intel_hdcp_adjust_hdcp_line_rekeying()
64 rekey_reg = CHICKEN_TRANS(display, hdcp->cpu_transcoder); in intel_hdcp_adjust_hdcp_line_rekeying()
69 intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit); in intel_hdcp_adjust_hdcp_line_rekeying()
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H A Dintel_ddi.c32 #include <drm/display/drm_dp_helper.h>
33 #include <drm/display/drm_scdc_helper.h>
119 static bool has_buf_trans_select(struct intel_display *display) in has_buf_trans_select() argument
121 return DISPLAY_VER(display) < 10 && !display->platform.broxton; in has_buf_trans_select()
124 static bool has_iboost(struct intel_display *display) in has_iboost() argument
126 return DISPLAY_VER(display) == 9 && !display->platform.broxton; in has_iboost()
137 struct intel_display *display = to_intel_display(encoder); in hsw_prepare_dp_ddi_buffers() local
144 if (drm_WARN_ON_ONCE(display->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
148 if (has_iboost(display) && in hsw_prepare_dp_ddi_buffers()
153 intel_de_write(display, DDI_BUF_TRANS_LO(port, i), in hsw_prepare_dp_ddi_buffers()
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H A Dvlv_dsi_regs.h14 #define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) argument
97 #define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_R… argument
107 #define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT,… argument
110 #define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MI… argument
146 #define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC… argument
169 #define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_T… argument
174 #define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_T… argument
179 #define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_T… argument
184 #define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DE… argument
189 #define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RE… argument
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H A Dintel_psr.c65 * Since Haswell Display controller supports Panel Self-Refresh on display
67 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
68 * when system is idle but display is on as it eliminates display refresh
70 * display is unchanged.
98 * When unmasked (nearly) all display register writes (eg. even
253 struct intel_display *display = to_intel_display(intel_dp); in panel_replay_global_enabled() local
256 display->params.enable_panel_replay; in panel_replay_global_enabled()
261 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_psr_error_bit_get() local
263 return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR : in psr_irq_psr_error_bit_get()
269 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_post_exit_bit_get() local
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H A Dintel_bios.c31 #include <drm/display/drm_dp_helper.h>
32 #include <drm/display/drm_dsc_helper.h>
54 * through other means. The configuration is mostly related to display
73 struct intel_display *display; member
152 bdb_find_section(struct intel_display *display, in bdb_find_section() argument
157 list_for_each_entry(entry, &display->vbt.bdb_blocks, node) { in bdb_find_section()
207 static size_t lfp_data_min_size(struct intel_display *display) in lfp_data_min_size() argument
212 ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS); in lfp_data_min_size()
367 static void *generate_lfp_data_ptrs(struct intel_display *display, in generate_lfp_data_ptrs() argument
381 if (display->vbt.version < 155) in generate_lfp_data_ptrs()
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H A Dintel_hdcp_gsc_message.c23 struct intel_display *display; in intel_hdcp_gsc_initiate_session() local
29 display = to_intel_display(dev); in intel_hdcp_gsc_initiate_session()
30 if (!display) { in intel_hdcp_gsc_initiate_session()
34 gsc_context = display->hdcp.gsc_context; in intel_hdcp_gsc_initiate_session()
47 byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, in intel_hdcp_gsc_initiate_session()
51 drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); in intel_hdcp_gsc_initiate_session()
56 drm_dbg_kms(display->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n", in intel_hdcp_gsc_initiate_session()
81 struct intel_display *display; in intel_hdcp_gsc_verify_receiver_cert_prepare_km() local
87 display = to_intel_display(dev); in intel_hdcp_gsc_verify_receiver_cert_prepare_km()
88 if (!display) { in intel_hdcp_gsc_verify_receiver_cert_prepare_km()
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H A Dskl_universal_plane.c240 static u8 icl_nv12_y_plane_mask(struct intel_display *display) in icl_nv12_y_plane_mask() argument
242 if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) in icl_nv12_y_plane_mask()
248 bool icl_is_nv12_y_plane(struct intel_display *display, in icl_is_nv12_y_plane() argument
251 return DISPLAY_VER(display) >= 11 && in icl_is_nv12_y_plane()
252 icl_nv12_y_plane_mask(display) & BIT(plane_id); in icl_is_nv12_y_plane()
260 bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id) in icl_is_hdr_plane() argument
262 return DISPLAY_VER(display) >= 11 && in icl_is_hdr_plane()
448 static bool skl_plane_has_fbc(struct intel_display *display, in skl_plane_has_fbc() argument
451 if ((DISPLAY_RUNTIME_INFO(display)->fbc_mask & BIT(fbc_id)) == 0) in skl_plane_has_fbc()
454 if (DISPLAY_VER(display) >= 20) in skl_plane_has_fbc()
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H A Dintel_cursor.c86 struct intel_display *display = to_intel_display(plane_state); in intel_cursor_check_surface() local
108 drm_dbg_kms(display->drm, in intel_cursor_check_surface()
122 if (HAS_GMCH(display) && rotation & DRM_MODE_ROTATE_180) { in intel_cursor_check_surface()
140 struct intel_display *display = to_intel_display(plane_state); in intel_check_cursor() local
148 drm_dbg_kms(display->drm, "[PLANE:%d:%s] cursor cannot be tiled\n", in intel_check_cursor()
229 struct intel_display *display = to_intel_display(plane_state); in i845_check_cursor() local
244 drm_dbg_kms(display->drm, in i845_check_cursor()
252 drm_WARN_ON(display->drm, plane_state->uapi.visible && in i845_check_cursor()
262 drm_dbg_kms(display->drm, "[PLANE:%d:%s] invalid cursor stride (%u)\n", in i845_check_cursor()
279 struct intel_display *display = to_intel_display(plane); in i845_cursor_update_arm() local
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H A Dintel_opregion.h37 int intel_opregion_setup(struct intel_display *display);
38 void intel_opregion_cleanup(struct intel_display *display);
40 void intel_opregion_register(struct intel_display *display);
41 void intel_opregion_unregister(struct intel_display *display);
43 void intel_opregion_resume(struct intel_display *display);
44 void intel_opregion_suspend(struct intel_display *display,
47 bool intel_opregion_asle_present(struct intel_display *display);
48 void intel_opregion_asle_intr(struct intel_display *display);
51 int intel_opregion_notify_adapter(struct intel_display *display,
53 int intel_opregion_get_panel_type(struct intel_display *display);
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H A Dintel_quirks.c14 static void intel_set_quirk(struct intel_display *display, enum intel_quirk_id quirk) in intel_set_quirk() argument
16 display->quirks.mask |= BIT(quirk); in intel_set_quirk()
27 static void quirk_ssc_force_disable(struct intel_display *display) in quirk_ssc_force_disable() argument
29 intel_set_quirk(display, QUIRK_LVDS_SSC_DISABLE); in quirk_ssc_force_disable()
30 drm_info(display->drm, "applying lvds SSC disable quirk\n"); in quirk_ssc_force_disable()
37 static void quirk_invert_brightness(struct intel_display *display) in quirk_invert_brightness() argument
39 intel_set_quirk(display, QUIRK_INVERT_BRIGHTNESS); in quirk_invert_brightness()
40 drm_info(display->drm, "applying inverted panel brightness quirk\n"); in quirk_invert_brightness()
44 static void quirk_backlight_present(struct intel_display *display) in quirk_backlight_present() argument
46 intel_set_quirk(display, QUIRK_BACKLIGHT_PRESENT); in quirk_backlight_present()
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H A Dintel_encoder.c35 struct intel_display *display = to_intel_display(encoder); in intel_encoder_link_check_queue_work() local
37 mod_delayed_work(display->wq.unordered, in intel_encoder_link_check_queue_work()
41 void intel_encoder_unblock_all_hpds(struct intel_display *display) in intel_encoder_unblock_all_hpds() argument
45 if (!HAS_DISPLAY(display)) in intel_encoder_unblock_all_hpds()
48 for_each_intel_encoder(display->drm, encoder) in intel_encoder_unblock_all_hpds()
52 void intel_encoder_block_all_hpds(struct intel_display *display) in intel_encoder_block_all_hpds() argument
56 if (!HAS_DISPLAY(display)) in intel_encoder_block_all_hpds()
59 for_each_intel_encoder(display->drm, encoder) in intel_encoder_block_all_hpds()
63 void intel_encoder_suspend_all(struct intel_display *display) in intel_encoder_suspend_all() argument
67 if (!HAS_DISPLAY(display)) in intel_encoder_suspend_all()
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H A Dintel_dp.c41 #include <drm/display/drm_dp_helper.h>
42 #include <drm/display/drm_dp_tunnel.h>
43 #include <drm/display/drm_dsc_helper.h>
44 #include <drm/display/drm_hdmi_helper.h>
160 struct intel_display *display = to_intel_display(intel_dp); in max_dprx_rate() local
174 if (intel_dp_is_edp(intel_dp) && intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2)) in max_dprx_rate()
294 struct intel_display *display = to_intel_display(intel_dp); in intel_dp_set_sink_rates() local
304 drm_err(display->drm, in intel_dp_set_sink_rates()
319 struct intel_display *display = to_intel_display(intel_dp); in intel_dp_set_max_sink_lane_count() local
333 drm_err(display->drm, in intel_dp_set_max_sink_lane_count()
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H A Dintel_cx0_phy.c40 struct intel_display *display = to_intel_display(encoder); in intel_encoder_is_c10phy() local
43 if (display->platform.pantherlake) { in intel_encoder_is_c10phy()
44 if (display->platform.pantherlake_wildcatlake) in intel_encoder_is_c10phy()
50 if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C) in intel_encoder_is_c10phy()
74 * by display and lane 1 is owned by USB. in intel_cx0_get_owned_lane_mask()
81 assert_dc_off(struct intel_display *display) in assert_dc_off() argument
85 enabled = intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF); in assert_dc_off()
86 drm_WARN_ON(display->drm, !enabled); in assert_dc_off()
91 struct intel_display *display = to_intel_display(encoder); in intel_cx0_program_msgbus_timer() local
95 intel_de_rmw(display, in intel_cx0_program_msgbus_timer()
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H A Dintel_lt_phy.c992 struct intel_display *display = to_intel_display(encoder); in intel_lt_phy_clear_status_p2p() local
994 intel_de_rmw(display, in intel_lt_phy_clear_status_p2p()
1000 assert_dc_off(struct intel_display *display) in assert_dc_off() argument
1004 enabled = intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF); in assert_dc_off()
1005 drm_WARN_ON(display->drm, !enabled); in assert_dc_off()
1013 struct intel_display *display = to_intel_display(encoder); in __intel_lt_phy_p2p_write_once() local
1019 if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), in __intel_lt_phy_p2p_write_once()
1022 drm_dbg_kms(display->drm, in __intel_lt_phy_p2p_write_once()
1029 intel_de_rmw(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane), 0, 0); in __intel_lt_phy_p2p_write_once()
1031 intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), in __intel_lt_phy_p2p_write_once()
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/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-display-engine.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml#
7 title: Allwinner A10 Display Engine Pipeline
14 The display engine pipeline (and its entry point, since it can be
18 The Allwinner A10 Display pipeline is composed of several components
22 display pipeline, when there are multiple components of the same
52 - allwinner,sun4i-a10-display-engine
53 - allwinner,sun5i-a10s-display-engine
54 - allwinner,sun5i-a13-display-engine
55 - allwinner,sun6i-a31-display-engine
56 - allwinner,sun6i-a31s-display-engine
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H A Dxylon,logicvc-display.yaml5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
8 title: Xylon LogiCVC display controller
14 The Xylon LogiCVC is a display controller that supports multiple layers.
32 - xylon,logicvc-3.02.a-display
33 - xylon,logicvc-4.01.a-display
67 xylon,display-interface:
79 description: Display output interface (C_DISPLAY_INTERFACE).
81 xylon,display-colorspace:
89 description: Display output colorspace (C_DISPLAY_COLOR_SPACE).
91 xylon,display-depth:
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/linux/drivers/staging/fbtft/
H A Dfbtft-core.c247 "%s: start_line=%u is larger than end_line=%u. Shouldn't happen, will do full display update\n", in fbtft_update_display()
255 …"%s: start_line=%u or end_line=%u is larger than max=%d. Shouldn't happen, will do full display up… in fbtft_update_display()
274 "%s: write_vmem failed to update display buffer\n", in fbtft_update_display()
291 "Display update: %ld kB/s, fps=%ld\n", in fbtft_update_display()
303 /* Mark display lines/area as dirty */ in fbtft_mkdirty()
311 /* Schedule deferred_io to update display (no-op if already on queue)*/ in fbtft_mkdirty()
325 /* set display line markers as clean */ in fbtft_deferred_io()
330 /* Mark display lines as dirty */ in fbtft_deferred_io()
477 * @display: pointer to structure describing the display
479 * @pdata: platform data for the display in use
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/linux/Documentation/devicetree/bindings/auxdisplay/
H A Dmodtronix,lcd2s.yaml7 title: Modtronix engineering LCD2S Character LCD Display
13 The LCD2S is a Character LCD Display manufactured by Modtronix Engineering.
14 The display supports a serial I2C and SPI interface. The driver currently
24 I2C bus address of the display.
26 display-height-chars:
27 description: Height of the display, in character cells.
32 display-width-chars:
33 description: Width of the display, in character cells.
41 - display-height-chars
42 - display-width-chars
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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra186-display.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
7 title: NVIDIA Tegra186 (and later) Display Hub
15 pattern: "^display-hub@[0-9a-f]+$"
19 - nvidia,tegra186-display
20 - nvidia,tegra194-display
44 - description: display hub reset
69 "^display@[0-9a-f]+$":
77 const: nvidia,tegra186-display
82 - description: display core clock
83 - description: display stream compression clock
[all …]
/linux/rust/kernel/
H A Dfmt.rs154 /// A copy of [`core::fmt::Display`] that allows us to implement it for foreign types.
156 /// Types should implement this trait rather than [`core::fmt::Display`]. Together with the
158 /// core) which do not implement [`core::fmt::Display`] directly.
161 pub trait Display {
162 /// Same as [`core::fmt::Display::fmt`].
166 impl<T: ?Sized + Display> Display for &T {
168 Display::fmt(*self, f)
172 impl<T: ?Sized + Display> core::fmt::Display fo
40 pub trait Display { global() interface
45 impl<T: ?Sized + Display> Display for &T { global() impl
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/linux/include/video/
H A Ds1d13xxxfb.h44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
48 #define S1DREG_LCD_DISP_VHEIGHT0 0x0038 /* LCD Vertical Display Height Register 0 */
49 #define S1DREG_LCD_DISP_VHEIGHT1 0x0039 /* LCD Vertical Display Height Register 1 */
50 #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
53 #define S1DREG_LCD_DISP_MODE 0x0040 /* LCD Display Mode Register */
55 #define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */
56 #define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */
57 #define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */
61 #define S1DREG_LCD_DISP_FIFO_HTC 0x004A /* LCD Display FIFO High Threshold Control Register */
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/linux/Documentation/devicetree/bindings/display/sprd/
H A Dsprd,display-subsystem.yaml4 $id: http://devicetree.org/schemas/display/sprd/sprd,display-subsystem.yaml#
14 DPU devices or other display interface nodes that comprise the
17 Unisoc's display pipeline have several components as below description,
18 multi display controllers and corresponding physical interfaces.
19 For different display scenarios, dpu0 and dpu1 maybe binding to different
23 dpu0 and dpu1 both binding to DSI for dual mipi-dsi display;
24 dpu0 binding to DSI for primary display, and dpu1 binding to DP for external display;
44 const: sprd,display-subsystem
51 Should contain a list of phandles pointing to display interface port
62 display-subsystem {
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