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/linux/drivers/gpu/drm/xe/
H A DMakefile208 # i915 Display compat #defines and #includes
211 -I$(srctree)/drivers/gpu/drm/i915/display/
213 # Rule to build display code shared with i915
214 $(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE
218 # Display code specific to xe
220 display/xe_display.o \
221 display/xe_display_bo.o \
222 display/xe_display_pcode.o \
223 display/xe_display_rpm.o \
224 display/xe_display_wa.o \
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.c60 * The display engine uses several different clocks to do its work. There
63 * are the core display clock (CDCLK) and RAWCLK.
65 * CDCLK clocks most of the display pipe logic, and thus its frequency
71 * to minimize power consumption for a given display configuration.
72 * Typically changes to the CDCLK frequency require all the display pipes
161 void (*get_cdclk)(struct intel_display *display,
163 void (*set_cdclk)(struct intel_display *display,
170 void intel_cdclk_get_cdclk(struct intel_display *display, in intel_cdclk_get_cdclk() argument
173 display->cdclk.funcs->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
176 static void intel_cdclk_set_cdclk(struct intel_display *display, in intel_cdclk_set_cdclk() argument
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H A Dintel_ddi.c32 #include <drm/display/drm_dp_helper.h>
33 #include <drm/display/drm_scdc_helper.h>
119 static bool has_buf_trans_select(struct intel_display *display) in has_buf_trans_select() argument
121 return DISPLAY_VER(display) < 10 && !display->platform.broxton; in has_buf_trans_select()
124 static bool has_iboost(struct intel_display *display) in has_iboost() argument
126 return DISPLAY_VER(display) == 9 && !display->platform.broxton; in has_iboost()
137 struct intel_display *display = to_intel_display(encoder); in hsw_prepare_dp_ddi_buffers() local
144 if (drm_WARN_ON_ONCE(display->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
148 if (has_iboost(display) && in hsw_prepare_dp_ddi_buffers()
153 intel_de_write(display, DDI_BUF_TRANS_LO(port, i), in hsw_prepare_dp_ddi_buffers()
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H A Dvlv_dsi_regs.h14 #define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) argument
97 #define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_R… argument
107 #define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT,… argument
110 #define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MI… argument
146 #define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC… argument
169 #define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_T… argument
174 #define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_T… argument
179 #define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_T… argument
184 #define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DE… argument
189 #define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RE… argument
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H A Dintel_hdcp_gsc_message.c23 struct intel_display *display; in intel_hdcp_gsc_initiate_session() local
29 display = to_intel_display(dev); in intel_hdcp_gsc_initiate_session()
30 if (!display) { in intel_hdcp_gsc_initiate_session()
34 gsc_context = display->hdcp.gsc_context; in intel_hdcp_gsc_initiate_session()
47 byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, in intel_hdcp_gsc_initiate_session()
51 drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); in intel_hdcp_gsc_initiate_session()
56 drm_dbg_kms(display->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n", in intel_hdcp_gsc_initiate_session()
81 struct intel_display *display; in intel_hdcp_gsc_verify_receiver_cert_prepare_km() local
87 display = to_intel_display(dev); in intel_hdcp_gsc_verify_receiver_cert_prepare_km()
88 if (!display) { in intel_hdcp_gsc_verify_receiver_cert_prepare_km()
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H A Dintel_opregion.h37 int intel_opregion_setup(struct intel_display *display);
38 void intel_opregion_cleanup(struct intel_display *display);
40 void intel_opregion_register(struct intel_display *display);
41 void intel_opregion_unregister(struct intel_display *display);
43 void intel_opregion_resume(struct intel_display *display);
44 void intel_opregion_suspend(struct intel_display *display,
47 bool intel_opregion_asle_present(struct intel_display *display);
48 void intel_opregion_asle_intr(struct intel_display *display);
51 int intel_opregion_notify_adapter(struct intel_display *display,
53 int intel_opregion_get_panel_type(struct intel_display *display);
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H A Dintel_encoder.c35 struct intel_display *display = to_intel_display(encoder); in intel_encoder_link_check_queue_work() local
37 mod_delayed_work(display->wq.unordered, in intel_encoder_link_check_queue_work()
41 void intel_encoder_unblock_all_hpds(struct intel_display *display) in intel_encoder_unblock_all_hpds() argument
45 if (!HAS_DISPLAY(display)) in intel_encoder_unblock_all_hpds()
48 for_each_intel_encoder(display->drm, encoder) in intel_encoder_unblock_all_hpds()
52 void intel_encoder_block_all_hpds(struct intel_display *display) in intel_encoder_block_all_hpds() argument
56 if (!HAS_DISPLAY(display)) in intel_encoder_block_all_hpds()
59 for_each_intel_encoder(display->drm, encoder) in intel_encoder_block_all_hpds()
63 void intel_encoder_suspend_all(struct intel_display *display) in intel_encoder_suspend_all() argument
67 if (!HAS_DISPLAY(display)) in intel_encoder_suspend_all()
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H A Dintel_dp_mst.c122 struct intel_display *display = to_intel_display(intel_dp); in intel_dp_mst_dec_active_streams() local
124 drm_dbg_kms(display->drm, "active MST streams %d -> %d\n", in intel_dp_mst_dec_active_streams()
127 if (drm_WARN_ON(display->drm, intel_dp->mst.active_streams == 0)) in intel_dp_mst_dec_active_streams()
135 struct intel_display *display = to_intel_display(intel_dp); in intel_dp_mst_inc_active_streams() local
137 drm_dbg_kms(display->drm, "active MST streams %d -> %d\n", in intel_dp_mst_inc_active_streams()
147 struct intel_display *display = to_intel_display(crtc_state); in intel_dp_mst_max_dpt_bpp() local
151 if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(display) >= 20 || !dsc) in intel_dp_mst_max_dpt_bpp()
164 * - DELL U3224KBA display in intel_dp_mst_max_dpt_bpp()
254 struct intel_display *display = to_intel_display(intel_dp); in intel_dp_mtp_tu_compute_config() local
267 drm_WARN_ON(display->drm, !dsc && (fxp_q4_to_frac(min_bpp_x16) || in intel_dp_mtp_tu_compute_config()
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H A Dintel_acpi.h14 void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display);
15 void intel_acpi_device_id_update(struct intel_display *display);
16 void intel_acpi_assign_connector_fwnodes(struct intel_display *display);
17 void intel_acpi_video_register(struct intel_display *display);
22 void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display) { return; } in intel_dsm_get_bios_data_funcs_supported() argument
24 void intel_acpi_device_id_update(struct intel_display *display) { return; } in intel_acpi_device_id_update() argument
26 void intel_acpi_assign_connector_fwnodes(struct intel_display *display) { return; } in intel_acpi_assign_connector_fwnodes() argument
28 void intel_acpi_video_register(struct intel_display *display) { return; } in intel_acpi_video_register() argument
/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-display-engine.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml#
7 title: Allwinner A10 Display Engine Pipeline
14 The display engine pipeline (and its entry point, since it can be
18 The Allwinner A10 Display pipeline is composed of several components
22 display pipeline, when there are multiple components of the same
52 - allwinner,sun4i-a10-display-engine
53 - allwinner,sun5i-a10s-display-engine
54 - allwinner,sun5i-a13-display-engine
55 - allwinner,sun6i-a31-display-engine
56 - allwinner,sun6i-a31s-display-engine
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H A Dxylon,logicvc-display.yaml5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
8 title: Xylon LogiCVC display controller
14 The Xylon LogiCVC is a display controller that supports multiple layers.
32 - xylon,logicvc-3.02.a-display
33 - xylon,logicvc-4.01.a-display
67 xylon,display-interface:
79 description: Display output interface (C_DISPLAY_INTERFACE).
81 xylon,display-colorspace:
89 description: Display output colorspace (C_DISPLAY_COLOR_SPACE).
91 xylon,display-depth:
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H A Dallwinner,sun4i-a10-display-backend.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-backend.yaml#
7 title: Allwinner A10 Display Engine Backend
14 The display engine backend exposes layers and sprites to the system.
19 - allwinner,sun4i-a10-display-backend
20 - allwinner,sun5i-a13-display-backend
21 - allwinner,sun6i-a31-display-backend
22 - allwinner,sun7i-a20-display-backend
23 - allwinner,sun8i-a23-display-backend
24 - allwinner,sun8i-a33-display-backend
25 - allwinner,sun9i-a80-display-backend
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H A Dcirrus,clps711x-fb.txt8 - display : phandle to a display node as described in
9 Documentation/devicetree/bindings/display/panel/display-timing.txt.
10 Additionally, the display node has to define properties:
25 display = <&display>;
28 display: display {
33 display-timings {
/linux/Documentation/devicetree/bindings/auxdisplay/
H A Dmodtronix,lcd2s.yaml7 title: Modtronix engineering LCD2S Character LCD Display
13 The LCD2S is a Character LCD Display manufactured by Modtronix Engineering.
14 The display supports a serial I2C and SPI interface. The driver currently
24 I2C bus address of the display.
26 display-height-chars:
27 description: Height of the display, in character cells.
32 display-width-chars:
33 description: Width of the display, in character cells.
41 - display-height-chars
42 - display-width-chars
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H A Dhit,hd44780.yaml14 LCDs that can display one or more lines of text. It exposes an M6800 bus
54 display-height-chars:
55 description: Height of the display, in character cells,
60 display-width-chars:
61 description: Width of the display, in character cells.
69 display-width-chars for displays with more than 2 lines).
79 - display-height-chars
80 - display-width-chars
87 display-controller {
97 display-height-chars = <2>;
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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra186-display.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
7 title: NVIDIA Tegra186 (and later) Display Hub
15 pattern: "^display-hub@[0-9a-f]+$"
19 - nvidia,tegra186-display
20 - nvidia,tegra194-display
44 - description: display hub reset
69 "^display@[0-9a-f]+$":
77 const: nvidia,tegra186-display
82 - description: display core clock
83 - description: display stream compression clock
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H A Dnvidia,tegra186-dc.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
7 title: NVIDIA Tegra186 (and later) Display Controller
15 pattern: "^display@[0-9a-f]+$"
30 - description: display controller pixel clock
38 - description: display controller reset
52 display controller; see ../interconnect/interconnect.txt
61 description: A list of phandles of outputs that this display
66 description: The number of the display controller head. This
85 # see nvidia,tegra186-display.yaml for examples
/linux/rust/kernel/
H A Dfmt.rs154 /// A copy of [`core::fmt::Display`] that allows us to implement it for foreign types.
156 /// Types should implement this trait rather than [`core::fmt::Display`]. Together with the
158 /// core) which do not implement [`core::fmt::Display`] directly.
161 pub trait Display {
162 /// Same as [`core::fmt::Display::fmt`].
166 impl<T: ?Sized + Display> Display for &T {
168 Display::fmt(*self, f)
172 impl<T: ?Sized + Display> core::fmt::Display fo
40 pub trait Display { global() interface
45 impl<T: ?Sized + Display> Display for &T { global() impl
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/linux/Documentation/devicetree/bindings/display/sprd/
H A Dsprd,display-subsystem.yaml4 $id: http://devicetree.org/schemas/display/sprd/sprd,display-subsystem.yaml#
14 DPU devices or other display interface nodes that comprise the
17 Unisoc's display pipeline have several components as below description,
18 multi display controllers and corresponding physical interfaces.
19 For different display scenarios, dpu0 and dpu1 maybe binding to different
23 dpu0 and dpu1 both binding to DSI for dual mipi-dsi display;
24 dpu0 binding to DSI for primary display, and dpu1 binding to DP for external display;
44 const: sprd,display-subsystem
51 Should contain a list of phandles pointing to display interface port
62 display-subsystem {
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/linux/include/video/
H A Ds1d13xxxfb.h44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
48 #define S1DREG_LCD_DISP_VHEIGHT0 0x0038 /* LCD Vertical Display Height Register 0 */
49 #define S1DREG_LCD_DISP_VHEIGHT1 0x0039 /* LCD Vertical Display Height Register 1 */
50 #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
53 #define S1DREG_LCD_DISP_MODE 0x0040 /* LCD Display Mode Register */
55 #define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */
56 #define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */
57 #define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */
61 #define S1DREG_LCD_DISP_FIFO_HTC 0x004A /* LCD Display FIFO High Threshold Control Register */
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/linux/drivers/auxdisplay/
H A Dline-display.c3 * Character line display core support
33 #include "line-display.h"
119 * linedisp_scroll() - scroll the display by a character
122 * Scroll the current message along the display by one character, rearming the
141 /* update the display */ in linedisp_scroll()
155 * @msg: the message to display
158 * Display a new message @msg on the display. @msg can be longer than the
159 * number of characters the display can display, in which case it will begin
160 * scrolling across the display.
180 /* Clear the display */ in linedisp_display()
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/linux/drivers/clk/qcom/
H A DKconfig23 tristate "Eliza Display Clock Controller"
27 Support for the display clock controllers on Eliza SoCs.
28 Say Y if you want to support display devices and functionality such as
49 tristate "Glymur Display Clock Controller"
53 Support for the display clock controllers on Qualcomm
55 Say Y if you want to support display devices and functionality such as
104 tristate "Kaanapali Display Clock Controller"
108 Support for the display clock controller on Qualcomm Technologies, Inc
110 Say Y if you want to support display devices and functionality such as
167 tristate "X1E80100 Display Clock Controller"
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/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sc7180-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-dpu.yaml#
7 title: Qualcomm Display DPU on SC7180
12 $ref: /schemas/display/msm/dpu-common.yaml#
35 - description: Display hf axi clock
36 - description: Display ahb clock
37 - description: Display rotator clock
38 - description: Display lut clock
39 - description: Display core clock
40 - description: Display vsync clock
41 - description: Display core throttle clock
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H A Dqcom,sm6115-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml#
7 title: Qualcomm Display DPU on SM6115
12 $ref: /schemas/display/msm/dpu-common.yaml#
30 - description: Display AXI
31 - description: Display AHB
32 - description: Display core
33 - description: Display lut
34 - description: Display rotator
35 - description: Display vsync
61 display-controller@5e01000 {
/linux/Documentation/devicetree/bindings/display/panel/
H A Ddisplay-timings.yaml4 $id: http://devicetree.org/schemas/display/panel/display-timings.yaml#
7 title: display timings
15 A display panel may be able to handle several display timings,
17 The display-timings node makes it possible to specify the timings
18 and to specify the timing that is native for the display.
22 const: display-timings
27 The default display timing is the one specified as native-mode.
46 display-timings {

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