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/linux/drivers/gpu/drm/i915/
H A DMakefile12 # Support compiling the display code separately for both i915 and xe
221 display/hsw_ips.o \
222 display/i9xx_display_sr.o \
223 display/i9xx_plane.o \
224 display/i9xx_wm.o \
225 display/intel_alpm.o \
226 display/intel_atomic.o \
227 display/intel_audio.o \
228 display/intel_bios.o \
229 display/intel_bo.o \
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_power.c207 static bool __intel_display_power_is_enabled(struct intel_display *display, in __intel_display_power_is_enabled() argument
213 if (intel_display_rpm_suspended(display)) in __intel_display_power_is_enabled()
218 for_each_power_domain_well_reverse(display, power_well, domain) { in __intel_display_power_is_enabled()
233 * @display: display device instance
248 bool intel_display_power_is_enabled(struct intel_display *display, in intel_display_power_is_enabled() argument
251 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_is_enabled()
255 ret = __intel_display_power_is_enabled(display, domain); in intel_display_power_is_enabled()
262 sanitize_target_dc_state(struct intel_display *display, in sanitize_target_dc_state() argument
265 struct i915_power_domains *power_domains = &display->power.domains; in sanitize_target_dc_state()
289 * @display: display device
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H A Dintel_dmc.c48 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
49 * engine to save and restore the state of display engine when it enter into
65 struct intel_display *display; member
87 static struct intel_dmc *display_to_dmc(struct intel_display *display) in display_to_dmc() argument
89 return display->dmc.dmc; in display_to_dmc()
92 static const char *dmc_firmware_param(struct intel_display *display) in dmc_firmware_param() argument
94 const char *p = display->params.dmc_firmware_path; in dmc_firmware_param()
99 static bool dmc_firmware_param_disabled(struct intel_display *display) in dmc_firmware_param_disabled() argument
101 const char *p = dmc_firmware_param(display); in dmc_firmware_param_disabled()
185 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) in dmc_firmware_default() argument
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H A Dintel_audio.c43 * DOC: High Definition Audio over HDMI and Display Port
46 * HDMI and Display Port. The audio programming sequences are divided into audio
191 static bool needs_wa_14020863754(struct intel_display *display) in needs_wa_14020863754() argument
193 return DISPLAY_VERx100(display) == 3000 || in needs_wa_14020863754()
194 DISPLAY_VERx100(display) == 2000 || in needs_wa_14020863754()
195 DISPLAY_VERx100(display) == 1401; in needs_wa_14020863754()
201 struct intel_display *display = to_intel_display(crtc_state); in audio_config_hdmi_pixel_clock() local
211 if (DISPLAY_VER(display) < 12 && adjusted_mode->crtc_clock > 148500) in audio_config_hdmi_pixel_clock()
215 drm_dbg_kms(display->drm, in audio_config_hdmi_pixel_clock()
221 drm_dbg_kms(display->drm, in audio_config_hdmi_pixel_clock()
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H A Dintel_psr.c59 * Since Haswell Display controller supports Panel Self-Refresh on display
61 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
62 * when system is idle but display is on as it eliminates display refresh
64 * display is unchanged.
108 * When unmasked (nearly) all display register writes (eg. even
263 struct intel_display *display = to_intel_display(intel_dp); in panel_replay_global_enabled() local
266 display->params.enable_panel_replay; in panel_replay_global_enabled()
271 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_psr_error_bit_get() local
273 return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR : in psr_irq_psr_error_bit_get()
279 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_post_exit_bit_get() local
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H A Dvlv_dsi_regs.h14 #define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) argument
97 #define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_R… argument
107 #define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT,… argument
110 #define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MI… argument
146 #define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC… argument
169 #define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_T… argument
174 #define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_T… argument
179 #define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_T… argument
184 #define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DE… argument
189 #define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RE… argument
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H A Dintel_frontbuffer.c51 * The other type of display power saving feature only cares about busyness
74 * @display: display device
84 static void frontbuffer_flush(struct intel_display *display, in frontbuffer_flush() argument
89 spin_lock(&display->fb_tracking.lock); in frontbuffer_flush()
90 frontbuffer_bits &= ~display->fb_tracking.busy_bits; in frontbuffer_flush()
91 spin_unlock(&display->fb_tracking.lock); in frontbuffer_flush()
96 trace_intel_frontbuffer_flush(display, frontbuffer_bits, origin); in frontbuffer_flush()
99 intel_td_flush(display); in frontbuffer_flush()
100 intel_drrs_flush(display, frontbuffer_bits); in frontbuffer_flush()
101 intel_psr_flush(display, frontbuffer_bits, origin); in frontbuffer_flush()
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H A Dintel_opregion.h37 int intel_opregion_setup(struct intel_display *display);
38 void intel_opregion_cleanup(struct intel_display *display);
40 void intel_opregion_register(struct intel_display *display);
41 void intel_opregion_unregister(struct intel_display *display);
43 void intel_opregion_resume(struct intel_display *display);
44 void intel_opregion_suspend(struct intel_display *display,
47 bool intel_opregion_asle_present(struct intel_display *display);
48 void intel_opregion_asle_intr(struct intel_display *display);
51 int intel_opregion_notify_adapter(struct intel_display *display,
53 int intel_opregion_get_panel_type(struct intel_display *display);
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H A Dintel_display_driver.h17 void intel_display_driver_init_hw(struct intel_display *display);
18 void intel_display_driver_early_probe(struct intel_display *display);
19 int intel_display_driver_probe_noirq(struct intel_display *display);
20 int intel_display_driver_probe_nogem(struct intel_display *display);
21 int intel_display_driver_probe(struct intel_display *display);
22 void intel_display_driver_register(struct intel_display *display);
23 void intel_display_driver_remove(struct intel_display *display);
24 void intel_display_driver_remove_noirq(struct intel_display *display);
25 void intel_display_driver_remove_nogem(struct intel_display *display);
26 void intel_display_driver_unregister(struct intel_display *display);
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H A Dintel_display_device.c27 __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info");
1384 * platforms. Their display will be probed automatically based on the IP version
1426 * Separate detection for no display cases to keep the display id array simple.
1503 const struct intel_display_device_info *display; member
1513 probe_gmdid_display(struct intel_display *display, struct intel_display_ip_ver *ip_ver) in probe_gmdid_display() argument
1515 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in probe_gmdid_display()
1523 drm_err(display->drm, in probe_gmdid_display()
1524 "Cannot map MMIO BAR to read display GMD_ID\n"); in probe_gmdid_display()
1532 drm_dbg_kms(display->drm, "Device doesn't have display\n"); in probe_gmdid_display()
1544 return gmdid_display_map[i].display; in probe_gmdid_display()
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H A Dintel_cx0_phy.c39 struct intel_display *display = to_intel_display(encoder); in intel_encoder_is_c10phy() local
42 if (display->platform.pantherlake) { in intel_encoder_is_c10phy()
43 if (display->platform.pantherlake_wildcatlake) in intel_encoder_is_c10phy()
49 if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C) in intel_encoder_is_c10phy()
73 * by display and lane 1 is owned by USB. in intel_cx0_get_owned_lane_mask()
80 assert_dc_off(struct intel_display *display) in assert_dc_off() argument
84 enabled = intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF); in assert_dc_off()
85 drm_WARN_ON(display->drm, !enabled); in assert_dc_off()
90 struct intel_display *display = to_intel_display(encoder); in intel_cx0_program_msgbus_timer() local
94 intel_de_rmw(display, in intel_cx0_program_msgbus_timer()
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H A Dintel_fb.c26 #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a)) argument
546 static bool plane_has_modifier(struct intel_display *display, in plane_has_modifier() argument
550 struct drm_i915_private *i915 = to_i915(display->drm); in plane_has_modifier()
552 if (!IS_DISPLAY_VER(display, md->display_ver.from, md->display_ver.until)) in plane_has_modifier()
567 (GRAPHICS_VER(i915) < 20 || !display->platform.dgfx)) in plane_has_modifier()
571 (GRAPHICS_VER(i915) < 20 || display->platform.dgfx)) in plane_has_modifier()
579 * @display: display instance
583 * Returns the list of modifiers allowed by the @display platform and @plane_caps.
586 u64 *intel_fb_plane_get_modifiers(struct intel_display *display, in intel_fb_plane_get_modifiers() argument
594 if (plane_has_modifier(display, plane_caps, &intel_modifiers[i])) in intel_fb_plane_get_modifiers()
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/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-display-engine.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml#
7 title: Allwinner A10 Display Engine Pipeline
14 The display engine pipeline (and its entry point, since it can be
18 The Allwinner A10 Display pipeline is composed of several components
22 display pipeline, when there are multiple components of the same
52 - allwinner,sun4i-a10-display-engine
53 - allwinner,sun5i-a10s-display-engine
54 - allwinner,sun5i-a13-display-engine
55 - allwinner,sun6i-a31-display-engine
56 - allwinner,sun6i-a31s-display-engine
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H A Dxylon,logicvc-display.yaml5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
8 title: Xylon LogiCVC display controller
14 The Xylon LogiCVC is a display controller that supports multiple layers.
32 - xylon,logicvc-3.02.a-display
33 - xylon,logicvc-4.01.a-display
67 xylon,display-interface:
79 description: Display output interface (C_DISPLAY_INTERFACE).
81 xylon,display-colorspace:
89 description: Display output colorspace (C_DISPLAY_COLOR_SPACE).
91 xylon,display-depth:
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H A Dallwinner,sun4i-a10-display-frontend.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-frontend.yaml#
7 title: Allwinner A10 Display Engine Frontend
14 The display engine frontend does formats conversion, scaling,
20 - allwinner,sun4i-a10-display-frontend
21 - allwinner,sun5i-a13-display-frontend
22 - allwinner,sun6i-a31-display-frontend
23 - allwinner,sun7i-a20-display-frontend
24 - allwinner,sun8i-a23-display-frontend
25 - allwinner,sun8i-a33-display-frontend
26 - allwinner,sun9i-a80-display-frontend
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/linux/drivers/soc/sunxi/
H A Dsunxi_mbus.c13 * The display engine virtual devices are not strictly speaking
18 "allwinner,sun4i-a10-display-engine",
19 "allwinner,sun5i-a10s-display-engine",
20 "allwinner,sun5i-a13-display-engine",
21 "allwinner,sun6i-a31-display-engine",
22 "allwinner,sun6i-a31s-display-engine",
23 "allwinner,sun7i-a20-display-engine",
24 "allwinner,sun8i-a23-display-engine",
25 "allwinner,sun8i-a33-display-engine",
26 "allwinner,sun9i-a80-display-engine",
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/linux/drivers/staging/fbtft/
H A Dfbtft-core.c248 "%s: start_line=%u is larger than end_line=%u. Shouldn't happen, will do full display update\n", in fbtft_update_display()
256 …"%s: start_line=%u or end_line=%u is larger than max=%d. Shouldn't happen, will do full display up… in fbtft_update_display()
275 "%s: write_vmem failed to update display buffer\n", in fbtft_update_display()
292 "Display update: %ld kB/s, fps=%ld\n", in fbtft_update_display()
309 /* Mark display lines/area as dirty */ in fbtft_mkdirty()
317 /* Schedule deferred_io to update display (no-op if already on queue)*/ in fbtft_mkdirty()
331 /* set display line markers as clean */ in fbtft_deferred_io()
336 /* Mark display lines as dirty */ in fbtft_deferred_io()
481 * @display: pointer to structure describing the display
483 * @pdata: platform data for the display in use
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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra186-display.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
7 title: NVIDIA Tegra186 (and later) Display Hub
15 pattern: "^display-hub@[0-9a-f]+$"
19 - nvidia,tegra186-display
20 - nvidia,tegra194-display
44 - description: display hub reset
69 "^display@[0-9a-f]+$":
77 const: nvidia,tegra186-display
82 - description: display core clock
83 - description: display stream compression clock
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/linux/Documentation/devicetree/bindings/auxdisplay/
H A Dmodtronix,lcd2s.yaml7 title: Modtronix engineering LCD2S Character LCD Display
13 The LCD2S is a Character LCD Display manufactured by Modtronix Engineering.
14 The display supports a serial I2C and SPI interface. The driver currently
24 I2C bus address of the display.
26 display-height-chars:
27 description: Height of the display, in character cells.
32 display-width-chars:
33 description: Width of the display, in character cells.
41 - display-height-chars
42 - display-width-chars
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H A Dhit,hd44780.yaml14 LCDs that can display one or more lines of text. It exposes an M6800 bus
54 display-height-chars:
55 description: Height of the display, in character cells,
60 display-width-chars:
61 description: Width of the display, in character cells.
69 display-width-chars for displays with more than 2 lines).
79 - display-height-chars
80 - display-width-chars
87 display-controller {
97 display-height-chars = <2>;
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/linux/drivers/acpi/acpica/
H A Dutbuffer.c22 * display - BYTE, WORD, DWORD, or QWORD display:
27 * base_offset - Beginning buffer offset (display only)
34 void acpi_ut_dump_buffer(u8 *buffer, u32 count, u32 display, u32 base_offset) in acpi_ut_dump_buffer() argument
40 u32 display_data_only = display & DB_DISPLAY_DATA_ONLY; in acpi_ut_dump_buffer()
42 display &= ~DB_DISPLAY_DATA_ONLY; in acpi_ut_dump_buffer()
49 display = DB_BYTE_DISPLAY; in acpi_ut_dump_buffer()
69 acpi_os_printf("%*s", ((display * 2) + 1), " "); in acpi_ut_dump_buffer()
70 j += display; in acpi_ut_dump_buffer()
74 switch (display) { in acpi_ut_dump_buffer()
76 default: /* Default is BYTE display */ in acpi_ut_dump_buffer()
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/linux/include/video/
H A Ds1d13xxxfb.h44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
48 #define S1DREG_LCD_DISP_VHEIGHT0 0x0038 /* LCD Vertical Display Height Register 0 */
49 #define S1DREG_LCD_DISP_VHEIGHT1 0x0039 /* LCD Vertical Display Height Register 1 */
50 #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
53 #define S1DREG_LCD_DISP_MODE 0x0040 /* LCD Display Mode Register */
55 #define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */
56 #define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */
57 #define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */
61 #define S1DREG_LCD_DISP_FIFO_HTC 0x004A /* LCD Display FIFO High Threshold Control Register */
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/linux/drivers/auxdisplay/
H A Dline-display.c3 * Character line display core support
30 #include "line-display.h"
35 * linedisp_scroll() - scroll the display by a character
38 * Scroll the current message along the display by one character, rearming the
57 /* update the display */ in linedisp_scroll()
72 * @msg: the message to display
75 * Display a new message @msg on the display. @msg can be longer than the
76 * number of characters the display can display, in which case it will begin
77 * scrolling across the display.
97 /* Clear the display */ in linedisp_display()
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/linux/Documentation/devicetree/bindings/display/sprd/
H A Dsprd,display-subsystem.yaml4 $id: http://devicetree.org/schemas/display/sprd/sprd,display-subsystem.yaml#
14 DPU devices or other display interface nodes that comprise the
17 Unisoc's display pipeline have several components as below description,
18 multi display controllers and corresponding physical interfaces.
19 For different display scenarios, dpu0 and dpu1 maybe binding to different
23 dpu0 and dpu1 both binding to DSI for dual mipi-dsi display;
24 dpu0 binding to DSI for primary display, and dpu1 binding to DP for external display;
44 const: sprd,display-subsystem
51 Should contain a list of phandles pointing to display interface port
62 display-subsystem {
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/linux/drivers/clk/qcom/
H A DKconfig23 tristate "GLYMUR Display Clock Controller"
27 Support for the display clock controllers on Qualcomm
29 Say Y if you want to support display devices and functionality such as
58 tristate "X1E80100 Display Clock Controller"
62 Support for the two display clock controllers on Qualcomm
64 Say Y if you want to support display devices and functionality such as
206 Say Y if you want to support multimedia devices such as display,
351 SD/eMMC, display, graphics, camera etc.
359 SD/eMMC, display, graphics, camera etc.
369 SD/eMMC, display, graphics, camera etc.
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