Lines Matching full:display
48 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
49 * engine to save and restore the state of display engine when it enter into
65 struct intel_display *display; member
87 static struct intel_dmc *display_to_dmc(struct intel_display *display) in display_to_dmc() argument
89 return display->dmc.dmc; in display_to_dmc()
92 static const char *dmc_firmware_param(struct intel_display *display) in dmc_firmware_param() argument
94 const char *p = display->params.dmc_firmware_path; in dmc_firmware_param()
99 static bool dmc_firmware_param_disabled(struct intel_display *display) in dmc_firmware_param_disabled() argument
101 const char *p = dmc_firmware_param(display); in dmc_firmware_param_disabled()
185 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) in dmc_firmware_default() argument
189 if (DISPLAY_VERx100(display) == 3002) { in dmc_firmware_default()
192 } else if (DISPLAY_VERx100(display) == 3000) { in dmc_firmware_default()
195 } else if (DISPLAY_VERx100(display) == 2000) { in dmc_firmware_default()
198 } else if (DISPLAY_VERx100(display) == 1401) { in dmc_firmware_default()
201 } else if (DISPLAY_VERx100(display) == 1400) { in dmc_firmware_default()
204 } else if (display->platform.dg2) { in dmc_firmware_default()
207 } else if (display->platform.alderlake_p) { in dmc_firmware_default()
210 } else if (display->platform.alderlake_s) { in dmc_firmware_default()
213 } else if (display->platform.dg1) { in dmc_firmware_default()
216 } else if (display->platform.rocketlake) { in dmc_firmware_default()
219 } else if (display->platform.tigerlake) { in dmc_firmware_default()
222 } else if (DISPLAY_VER(display) == 11) { in dmc_firmware_default()
225 } else if (display->platform.geminilake) { in dmc_firmware_default()
228 } else if (display->platform.kabylake || in dmc_firmware_default()
229 display->platform.coffeelake || in dmc_firmware_default()
230 display->platform.cometlake) { in dmc_firmware_default()
233 } else if (display->platform.skylake) { in dmc_firmware_default()
236 } else if (display->platform.broxton) { in dmc_firmware_default()
403 static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id) in has_dmc_id_fw() argument
405 struct intel_dmc *dmc = display_to_dmc(display); in has_dmc_id_fw()
410 bool intel_dmc_has_payload(struct intel_display *display) in intel_dmc_has_payload() argument
412 return has_dmc_id_fw(display, DMC_FW_MAIN); in intel_dmc_has_payload()
416 intel_get_stepping_info(struct intel_display *display, in intel_get_stepping_info() argument
419 const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display)); in intel_get_stepping_info()
426 static void gen9_set_dc_state_debugmask(struct intel_display *display) in gen9_set_dc_state_debugmask() argument
429 intel_de_rmw(display, DC_STATE_DEBUG, 0, in gen9_set_dc_state_debugmask()
431 intel_de_posting_read(display, DC_STATE_DEBUG); in gen9_set_dc_state_debugmask()
434 static void disable_event_handler(struct intel_display *display, in disable_event_handler() argument
437 intel_de_write(display, ctl_reg, in disable_event_handler()
442 intel_de_write(display, htp_reg, 0); in disable_event_handler()
445 static void disable_all_event_handlers(struct intel_display *display, in disable_all_event_handlers() argument
451 if (DISPLAY_VER(display) < 12) in disable_all_event_handlers()
454 if (!has_dmc_id_fw(display, dmc_id)) in disable_all_event_handlers()
458 disable_event_handler(display, in disable_all_event_handlers()
459 DMC_EVT_CTL(display, dmc_id, handler), in disable_all_event_handlers()
460 DMC_EVT_HTP(display, dmc_id, handler)); in disable_all_event_handlers()
463 static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable) in adlp_pipedmc_clock_gating_wa() argument
476 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), in adlp_pipedmc_clock_gating_wa()
480 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), in adlp_pipedmc_clock_gating_wa()
484 static void mtl_pipedmc_clock_gating_wa(struct intel_display *display) in mtl_pipedmc_clock_gating_wa() argument
491 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, in mtl_pipedmc_clock_gating_wa()
496 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) in pipedmc_clock_gating_wa() argument
498 if (display->platform.meteorlake && enable) in pipedmc_clock_gating_wa()
499 mtl_pipedmc_clock_gating_wa(display); in pipedmc_clock_gating_wa()
500 else if (DISPLAY_VER(display) == 13) in pipedmc_clock_gating_wa()
501 adlp_pipedmc_clock_gating_wa(display, enable); in pipedmc_clock_gating_wa()
504 static u32 pipedmc_interrupt_mask(struct intel_display *display) in pipedmc_interrupt_mask() argument
524 static bool is_dmc_evt_ctl_reg(struct intel_display *display, in is_dmc_evt_ctl_reg() argument
528 u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); in is_dmc_evt_ctl_reg()
529 u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); in is_dmc_evt_ctl_reg()
534 static bool is_dmc_evt_htp_reg(struct intel_display *display, in is_dmc_evt_htp_reg() argument
538 u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); in is_dmc_evt_htp_reg()
539 u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); in is_dmc_evt_htp_reg()
544 static bool is_event_handler(struct intel_display *display, in is_event_handler() argument
549 return is_dmc_evt_ctl_reg(display, dmc_id, reg) && in is_event_handler()
553 static bool fixup_dmc_evt(struct intel_display *display, in fixup_dmc_evt() argument
558 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl)) in fixup_dmc_evt()
561 if (!is_dmc_evt_htp_reg(display, dmc_id, reg_htp)) in fixup_dmc_evt()
565 if (i915_mmio_reg_offset(reg_ctl) - i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) != in fixup_dmc_evt()
566 i915_mmio_reg_offset(reg_htp) - i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0))) in fixup_dmc_evt()
573 if (display->platform.alderlake_s && dmc_id == DMC_FW_MAIN && in fixup_dmc_evt()
574 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) { in fixup_dmc_evt()
583 static bool disable_dmc_evt(struct intel_display *display, in disable_dmc_evt() argument
587 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) in disable_dmc_evt()
595 if (display->platform.tigerlake && in disable_dmc_evt()
596 is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data)) in disable_dmc_evt()
600 if ((display->platform.tigerlake || display->platform.alderlake_s) && in disable_dmc_evt()
601 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg, data)) in disable_dmc_evt()
607 static u32 dmc_mmiodata(struct intel_display *display, in dmc_mmiodata() argument
611 if (disable_dmc_evt(display, dmc_id, in dmc_mmiodata()
619 static void dmc_load_mmio(struct intel_display *display, enum intel_dmc_id dmc_id) in dmc_load_mmio() argument
621 struct intel_dmc *dmc = display_to_dmc(display); in dmc_load_mmio()
625 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i], in dmc_load_mmio()
626 dmc_mmiodata(display, dmc, dmc_id, i)); in dmc_load_mmio()
630 static void dmc_load_program(struct intel_display *display, enum intel_dmc_id dmc_id) in dmc_load_program() argument
632 struct intel_dmc *dmc = display_to_dmc(display); in dmc_load_program()
635 disable_all_event_handlers(display, dmc_id); in dmc_load_program()
640 intel_de_write_fw(display, in dmc_load_program()
647 dmc_load_mmio(display, dmc_id); in dmc_load_program()
650 static void assert_dmc_loaded(struct intel_display *display, in assert_dmc_loaded() argument
653 struct intel_dmc *dmc = display_to_dmc(display); in assert_dmc_loaded()
657 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) in assert_dmc_loaded()
660 found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0)); in assert_dmc_loaded()
663 drm_WARN(display->drm, found != expected, in assert_dmc_loaded()
670 found = intel_de_read(display, reg); in assert_dmc_loaded()
671 expected = dmc_mmiodata(display, dmc, dmc_id, i); in assert_dmc_loaded()
674 if (is_dmc_evt_ctl_reg(display, dmc_id, reg)) { in assert_dmc_loaded()
679 drm_WARN(display->drm, found != expected, in assert_dmc_loaded()
685 void assert_main_dmc_loaded(struct intel_display *display) in assert_main_dmc_loaded() argument
687 assert_dmc_loaded(display, DMC_FW_MAIN); in assert_main_dmc_loaded()
690 static bool need_pipedmc_load_program(struct intel_display *display) in need_pipedmc_load_program() argument
693 return DISPLAY_VER(display) == 12; in need_pipedmc_load_program()
696 static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe) in need_pipedmc_load_mmio() argument
703 if (DISPLAY_VER(display) == 30) in need_pipedmc_load_mmio()
712 if (DISPLAY_VER(display) == 20) in need_pipedmc_load_mmio()
719 if (display->platform.battlemage) in need_pipedmc_load_mmio()
728 if (display->platform.dg2) in need_pipedmc_load_mmio()
736 if (IS_DISPLAY_VER(display, 13, 14)) in need_pipedmc_load_mmio()
744 struct intel_display *display = to_intel_display(crtc_state); in can_enable_pipedmc() local
751 if (DISPLAY_VER(display) == 12 && crtc_state->has_psr) in can_enable_pipedmc()
759 struct intel_display *display = to_intel_display(crtc_state); in intel_dmc_enable_pipe() local
764 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) in intel_dmc_enable_pipe()
772 if (need_pipedmc_load_program(display)) in intel_dmc_enable_pipe()
773 dmc_load_program(display, dmc_id); in intel_dmc_enable_pipe()
774 else if (need_pipedmc_load_mmio(display, pipe)) in intel_dmc_enable_pipe()
775 dmc_load_mmio(display, dmc_id); in intel_dmc_enable_pipe()
777 assert_dmc_loaded(display, dmc_id); in intel_dmc_enable_pipe()
779 if (DISPLAY_VER(display) >= 20) { in intel_dmc_enable_pipe()
780 intel_flipq_reset(display, pipe); in intel_dmc_enable_pipe()
782 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); in intel_dmc_enable_pipe()
783 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display)); in intel_dmc_enable_pipe()
786 if (DISPLAY_VER(display) >= 14) in intel_dmc_enable_pipe()
787 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); in intel_dmc_enable_pipe()
789 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); in intel_dmc_enable_pipe()
794 struct intel_display *display = to_intel_display(crtc_state); in intel_dmc_disable_pipe() local
799 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) in intel_dmc_disable_pipe()
802 if (DISPLAY_VER(display) >= 14) in intel_dmc_disable_pipe()
803 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); in intel_dmc_disable_pipe()
805 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); in intel_dmc_disable_pipe()
807 if (DISPLAY_VER(display) >= 20) { in intel_dmc_disable_pipe()
808 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0); in intel_dmc_disable_pipe()
809 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); in intel_dmc_disable_pipe()
811 intel_flipq_reset(display, pipe); in intel_dmc_disable_pipe()
815 static void dmc_configure_event(struct intel_display *display, in dmc_configure_event() argument
820 struct intel_dmc *dmc = display_to_dmc(display); in dmc_configure_event()
828 if (!is_event_handler(display, dmc_id, event_id, reg, data)) in dmc_configure_event()
831 intel_de_write(display, reg, enable ? data : dmc_evt_ctl_disable()); in dmc_configure_event()
835 drm_WARN_ONCE(display->drm, num_handlers != 1, in dmc_configure_event()
842 * @display: display instance
849 void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, in intel_dmc_block_pkgc() argument
852 intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe), in intel_dmc_block_pkgc()
860 * @display: display instance
867 void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, in intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() argument
872 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable); in intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank()
877 * @display: display instance
880 * Everytime display comes back from low power state this function is called to
883 void intel_dmc_load_program(struct intel_display *display) in intel_dmc_load_program() argument
885 struct i915_power_domains *power_domains = &display->power.domains; in intel_dmc_load_program()
888 if (!intel_dmc_has_payload(display)) in intel_dmc_load_program()
891 assert_display_rpm_held(display); in intel_dmc_load_program()
893 pipedmc_clock_gating_wa(display, true); in intel_dmc_load_program()
896 dmc_load_program(display, dmc_id); in intel_dmc_load_program()
897 assert_dmc_loaded(display, dmc_id); in intel_dmc_load_program()
900 if (DISPLAY_VER(display) >= 20) in intel_dmc_load_program()
901 intel_de_write(display, DMC_FQ_W2_PTS_CFG_SEL, in intel_dmc_load_program()
909 gen9_set_dc_state_debugmask(display); in intel_dmc_load_program()
911 pipedmc_clock_gating_wa(display, false); in intel_dmc_load_program()
916 * @display: display instance
919 * inactive after the display is uninitialized.
921 void intel_dmc_disable_program(struct intel_display *display) in intel_dmc_disable_program() argument
925 if (!intel_dmc_has_payload(display)) in intel_dmc_disable_program()
928 pipedmc_clock_gating_wa(display, true); in intel_dmc_disable_program()
931 disable_all_event_handlers(display, dmc_id); in intel_dmc_disable_program()
933 pipedmc_clock_gating_wa(display, false); in intel_dmc_disable_program()
963 struct intel_display *display = dmc->display; in dmc_set_fw_offset() local
971 drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id); in dmc_set_fw_offset()
993 struct intel_display *display = dmc->display; in dmc_mmio_addr_sanity_check() local
1003 } else if (DISPLAY_VER(display) >= 13) { in dmc_mmio_addr_sanity_check()
1006 } else if (DISPLAY_VER(display) >= 12) { in dmc_mmio_addr_sanity_check()
1010 drm_warn(display->drm, "Unknown mmio range for sanity check"); in dmc_mmio_addr_sanity_check()
1026 struct intel_display *display = dmc->display; in parse_dmc_fw_header() local
1074 drm_err(display->drm, "Unknown DMC fw header version: %u\n", in parse_dmc_fw_header()
1080 drm_err(display->drm, "DMC firmware has wrong dmc header length " in parse_dmc_fw_header()
1087 drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); in parse_dmc_fw_header()
1093 drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n"); in parse_dmc_fw_header()
1097 drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id); in parse_dmc_fw_header()
1109 if (!fixup_dmc_evt(display, dmc_id, in parse_dmc_fw_header()
1114 drm_dbg_kms(display->drm, in parse_dmc_fw_header()
1118 drm_dbg_kms(display->drm, in parse_dmc_fw_header()
1125 drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", in parse_dmc_fw_header()
1127 is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : in parse_dmc_fw_header()
1128 is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", in parse_dmc_fw_header()
1129 disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], in parse_dmc_fw_header()
1143 drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size); in parse_dmc_fw_header()
1158 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); in parse_dmc_fw_header()
1168 struct intel_display *display = dmc->display; in parse_dmc_fw_package() local
1181 drm_err(display->drm, "DMC firmware has unknown header version %u\n", in parse_dmc_fw_package()
1195 drm_err(display->drm, "DMC firmware has wrong package header length " in parse_dmc_fw_package()
1213 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); in parse_dmc_fw_package()
1222 struct intel_display *display = dmc->display; in parse_dmc_fw_css() local
1225 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); in parse_dmc_fw_css()
1231 drm_err(display->drm, "DMC firmware has wrong CSS header length " in parse_dmc_fw_css()
1244 struct intel_display *display = dmc->display; in parse_dmc_fw() local
1249 const struct stepping_info *si = intel_get_stepping_info(display, &display_info); in parse_dmc_fw()
1279 drm_err(display->drm, "Reading beyond the fw_size\n"); in parse_dmc_fw()
1287 if (!intel_dmc_has_payload(display)) { in parse_dmc_fw()
1288 drm_err(display->drm, "DMC firmware main program not found\n"); in parse_dmc_fw()
1295 static void intel_dmc_runtime_pm_get(struct intel_display *display) in intel_dmc_runtime_pm_get() argument
1297 drm_WARN_ON(display->drm, display->dmc.wakeref); in intel_dmc_runtime_pm_get()
1298 display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); in intel_dmc_runtime_pm_get()
1301 static void intel_dmc_runtime_pm_put(struct intel_display *display) in intel_dmc_runtime_pm_put() argument
1304 fetch_and_zero(&display->dmc.wakeref); in intel_dmc_runtime_pm_put()
1306 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); in intel_dmc_runtime_pm_put()
1309 static const char *dmc_fallback_path(struct intel_display *display) in dmc_fallback_path() argument
1311 if (display->platform.alderlake_p) in dmc_fallback_path()
1320 struct intel_display *display = dmc->display; in dmc_load_work_fn() local
1325 err = request_firmware(&fw, dmc->fw_path, display->drm->dev); in dmc_load_work_fn()
1327 if (err == -ENOENT && !dmc_firmware_param(display)) { in dmc_load_work_fn()
1328 fallback_path = dmc_fallback_path(display); in dmc_load_work_fn()
1330 drm_dbg_kms(display->drm, "%s not found, falling back to %s\n", in dmc_load_work_fn()
1332 err = request_firmware(&fw, fallback_path, display->drm->dev); in dmc_load_work_fn()
1339 drm_notice(display->drm, in dmc_load_work_fn()
1342 drm_notice(display->drm, "DMC firmware homepage: %s", in dmc_load_work_fn()
1349 drm_notice(display->drm, in dmc_load_work_fn()
1355 intel_dmc_load_program(display); in dmc_load_work_fn()
1356 intel_dmc_runtime_pm_put(display); in dmc_load_work_fn()
1358 drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n", in dmc_load_work_fn()
1368 * @display: display instance
1370 * This function is called at the time of loading the display driver to read
1373 void intel_dmc_init(struct intel_display *display) in intel_dmc_init() argument
1377 if (!HAS_DMC(display)) in intel_dmc_init()
1388 intel_dmc_runtime_pm_get(display); in intel_dmc_init()
1394 dmc->display = display; in intel_dmc_init()
1398 dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size); in intel_dmc_init()
1400 if (dmc_firmware_param_disabled(display)) { in intel_dmc_init()
1401 drm_info(display->drm, "Disabling DMC firmware and runtime PM\n"); in intel_dmc_init()
1405 if (dmc_firmware_param(display)) in intel_dmc_init()
1406 dmc->fw_path = dmc_firmware_param(display); in intel_dmc_init()
1409 drm_dbg_kms(display->drm, in intel_dmc_init()
1414 display->dmc.dmc = dmc; in intel_dmc_init()
1416 drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path); in intel_dmc_init()
1417 queue_work(display->wq.unordered, &dmc->work); in intel_dmc_init()
1427 * @display: display instance
1433 void intel_dmc_suspend(struct intel_display *display) in intel_dmc_suspend() argument
1435 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_suspend()
1437 if (!HAS_DMC(display)) in intel_dmc_suspend()
1444 if (!intel_dmc_has_payload(display)) in intel_dmc_suspend()
1445 intel_dmc_runtime_pm_put(display); in intel_dmc_suspend()
1448 void intel_dmc_wait_fw_load(struct intel_display *display) in intel_dmc_wait_fw_load() argument
1450 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_wait_fw_load()
1452 if (!HAS_DMC(display)) in intel_dmc_wait_fw_load()
1461 * @display: display instance
1466 void intel_dmc_resume(struct intel_display *display) in intel_dmc_resume() argument
1468 if (!HAS_DMC(display)) in intel_dmc_resume()
1475 if (!intel_dmc_has_payload(display)) in intel_dmc_resume()
1476 intel_dmc_runtime_pm_get(display); in intel_dmc_resume()
1481 * @display: display instance
1486 void intel_dmc_fini(struct intel_display *display) in intel_dmc_fini() argument
1488 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_fini()
1491 if (!HAS_DMC(display)) in intel_dmc_fini()
1494 intel_dmc_suspend(display); in intel_dmc_fini()
1495 drm_WARN_ON(display->drm, display->dmc.wakeref); in intel_dmc_fini()
1502 display->dmc.dmc = NULL; in intel_dmc_fini()
1512 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display) in intel_dmc_snapshot_capture() argument
1514 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_snapshot_capture()
1517 if (!HAS_DMC(display)) in intel_dmc_snapshot_capture()
1525 snapshot->loaded = intel_dmc_has_payload(display); in intel_dmc_snapshot_capture()
1545 void intel_dmc_update_dc6_allowed_count(struct intel_display *display, in intel_dmc_update_dc6_allowed_count() argument
1548 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_update_dc6_allowed_count()
1551 if (DISPLAY_VER(dmc->display) < 14) in intel_dmc_update_dc6_allowed_count()
1554 dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT); in intel_dmc_update_dc6_allowed_count()
1562 static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count) in intel_dmc_get_dc6_allowed_count() argument
1564 struct i915_power_domains *power_domains = &display->power.domains; in intel_dmc_get_dc6_allowed_count()
1565 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_get_dc6_allowed_count()
1568 if (DISPLAY_VER(display) < 14) in intel_dmc_get_dc6_allowed_count()
1572 dc6_enabled = intel_de_read(display, DC_STATE_EN) & in intel_dmc_get_dc6_allowed_count()
1575 intel_dmc_update_dc6_allowed_count(display, false); in intel_dmc_get_dc6_allowed_count()
1585 struct intel_display *display = m->private; in intel_dmc_debugfs_status_show() local
1586 struct intel_dmc *dmc = display_to_dmc(display); in intel_dmc_debugfs_status_show()
1591 if (!HAS_DMC(display)) in intel_dmc_debugfs_status_show()
1594 wakeref = intel_display_rpm_get(display); in intel_dmc_debugfs_status_show()
1598 str_yes_no(intel_dmc_has_payload(display))); in intel_dmc_debugfs_status_show()
1601 str_yes_no(DISPLAY_VER(display) >= 12)); in intel_dmc_debugfs_status_show()
1603 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA))); in intel_dmc_debugfs_status_show()
1605 str_yes_no(display->platform.alderlake_p || in intel_dmc_debugfs_status_show()
1606 DISPLAY_VER(display) >= 14)); in intel_dmc_debugfs_status_show()
1608 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB))); in intel_dmc_debugfs_status_show()
1610 if (!intel_dmc_has_payload(display)) in intel_dmc_debugfs_status_show()
1616 if (DISPLAY_VER(display) >= 12) { in intel_dmc_debugfs_status_show()
1619 if (display->platform.dgfx || DISPLAY_VER(display) >= 14) { in intel_dmc_debugfs_status_show()
1629 intel_de_read(display, dc3co_reg)); in intel_dmc_debugfs_status_show()
1631 dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT : in intel_dmc_debugfs_status_show()
1633 if (!display->platform.geminilake && !display->platform.broxton) in intel_dmc_debugfs_status_show()
1637 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg)); in intel_dmc_debugfs_status_show()
1639 if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count)) in intel_dmc_debugfs_status_show()
1644 intel_de_read(display, dc6_reg)); in intel_dmc_debugfs_status_show()
1647 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); in intel_dmc_debugfs_status_show()
1651 intel_de_read(display, DMC_SSP_BASE)); in intel_dmc_debugfs_status_show()
1652 seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL)); in intel_dmc_debugfs_status_show()
1654 intel_display_rpm_put(display, wakeref); in intel_dmc_debugfs_status_show()
1661 void intel_dmc_debugfs_register(struct intel_display *display) in intel_dmc_debugfs_register() argument
1663 debugfs_create_file("i915_dmc_info", 0444, display->drm->debugfs_root, in intel_dmc_debugfs_register()
1664 display, &intel_dmc_debugfs_status_fops); in intel_dmc_debugfs_register()
1667 void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe) in intel_pipedmc_irq_handler() argument
1669 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in intel_pipedmc_irq_handler()
1672 if (DISPLAY_VER(display) >= 20) { in intel_pipedmc_irq_handler()
1673 tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe)); in intel_pipedmc_irq_handler()
1674 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp); in intel_pipedmc_irq_handler()
1677 spin_lock(&display->drm->event_lock); in intel_pipedmc_irq_handler()
1690 spin_unlock(&display->drm->event_lock); in intel_pipedmc_irq_handler()
1694 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC ATS fault\n", in intel_pipedmc_irq_handler()
1697 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC GTT fault\n", in intel_pipedmc_irq_handler()
1700 drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC error\n", in intel_pipedmc_irq_handler()
1704 int_vector = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK; in intel_pipedmc_irq_handler()
1706 drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt vector 0x%x\n", in intel_pipedmc_irq_handler()
1713 struct intel_display *display = to_intel_display(crtc); in intel_pipedmc_enable_event() local
1716 dmc_configure_event(display, dmc_id, event, true); in intel_pipedmc_enable_event()
1722 struct intel_display *display = to_intel_display(crtc); in intel_pipedmc_disable_event() local
1725 dmc_configure_event(display, dmc_id, event, false); in intel_pipedmc_disable_event()
1730 struct intel_display *display = to_intel_display(crtc); in intel_pipedmc_start_mmioaddr() local
1731 struct intel_dmc *dmc = display_to_dmc(display); in intel_pipedmc_start_mmioaddr()