1fe8b45aaSThierry Reding# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2fe8b45aaSThierry Reding%YAML 1.2 3fe8b45aaSThierry Reding--- 4fe8b45aaSThierry Reding$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml# 5fe8b45aaSThierry Reding$schema: http://devicetree.org/meta-schemas/core.yaml# 6fe8b45aaSThierry Reding 7fe8b45aaSThierry Redingtitle: NVIDIA Tegra186 (and later) Display Hub 8fe8b45aaSThierry Reding 9fe8b45aaSThierry Redingmaintainers: 10fe8b45aaSThierry Reding - Thierry Reding <thierry.reding@gmail.com> 11fe8b45aaSThierry Reding - Jon Hunter <jonathanh@nvidia.com> 12fe8b45aaSThierry Reding 13fe8b45aaSThierry Redingproperties: 14fe8b45aaSThierry Reding $nodename: 15fe8b45aaSThierry Reding pattern: "^display-hub@[0-9a-f]+$" 16fe8b45aaSThierry Reding 17fe8b45aaSThierry Reding compatible: 18fe8b45aaSThierry Reding enum: 19fe8b45aaSThierry Reding - nvidia,tegra186-display 20fe8b45aaSThierry Reding - nvidia,tegra194-display 21fe8b45aaSThierry Reding 22fe8b45aaSThierry Reding '#address-cells': 23*6427569fSThierry Reding enum: [ 1, 2 ] 24fe8b45aaSThierry Reding 25fe8b45aaSThierry Reding '#size-cells': 26*6427569fSThierry Reding enum: [ 1, 2 ] 27fe8b45aaSThierry Reding 28fe8b45aaSThierry Reding reg: 29fe8b45aaSThierry Reding maxItems: 1 30fe8b45aaSThierry Reding 31fe8b45aaSThierry Reding interrupts: 32fe8b45aaSThierry Reding maxItems: 1 33fe8b45aaSThierry Reding 34fe8b45aaSThierry Reding clocks: 35fe8b45aaSThierry Reding minItems: 2 36fe8b45aaSThierry Reding maxItems: 3 37fe8b45aaSThierry Reding 38fe8b45aaSThierry Reding clock-names: 39fe8b45aaSThierry Reding minItems: 2 40fe8b45aaSThierry Reding maxItems: 3 41fe8b45aaSThierry Reding 42fe8b45aaSThierry Reding resets: 43fe8b45aaSThierry Reding items: 44fe8b45aaSThierry Reding - description: display hub reset 45fe8b45aaSThierry Reding - description: window group 0 reset 46fe8b45aaSThierry Reding - description: window group 1 reset 47fe8b45aaSThierry Reding - description: window group 2 reset 48fe8b45aaSThierry Reding - description: window group 3 reset 49fe8b45aaSThierry Reding - description: window group 4 reset 50fe8b45aaSThierry Reding - description: window group 5 reset 51fe8b45aaSThierry Reding 52fe8b45aaSThierry Reding reset-names: 53fe8b45aaSThierry Reding items: 54fe8b45aaSThierry Reding - const: misc 55fe8b45aaSThierry Reding - const: wgrp0 56fe8b45aaSThierry Reding - const: wgrp1 57fe8b45aaSThierry Reding - const: wgrp2 58fe8b45aaSThierry Reding - const: wgrp3 59fe8b45aaSThierry Reding - const: wgrp4 60fe8b45aaSThierry Reding - const: wgrp5 61fe8b45aaSThierry Reding 62fe8b45aaSThierry Reding power-domains: 63fe8b45aaSThierry Reding maxItems: 1 64fe8b45aaSThierry Reding 65fe8b45aaSThierry Reding ranges: 66fe8b45aaSThierry Reding maxItems: 1 67fe8b45aaSThierry Reding 68fe8b45aaSThierry RedingpatternProperties: 69fe8b45aaSThierry Reding "^display@[0-9a-f]+$": 70fe8b45aaSThierry Reding type: object 71fe8b45aaSThierry Reding 72fe8b45aaSThierry RedingallOf: 73fe8b45aaSThierry Reding - if: 74fe8b45aaSThierry Reding properties: 75fe8b45aaSThierry Reding compatible: 76fe8b45aaSThierry Reding contains: 77fe8b45aaSThierry Reding const: nvidia,tegra186-display 78fe8b45aaSThierry Reding then: 79fe8b45aaSThierry Reding properties: 80fe8b45aaSThierry Reding clocks: 81fe8b45aaSThierry Reding items: 82fe8b45aaSThierry Reding - description: display core clock 83fe8b45aaSThierry Reding - description: display stream compression clock 84fe8b45aaSThierry Reding - description: display hub clock 85fe8b45aaSThierry Reding 86fe8b45aaSThierry Reding clock-names: 87fe8b45aaSThierry Reding items: 88fe8b45aaSThierry Reding - const: disp 89fe8b45aaSThierry Reding - const: dsc 90fe8b45aaSThierry Reding - const: hub 91fe8b45aaSThierry Reding else: 92fe8b45aaSThierry Reding properties: 93fe8b45aaSThierry Reding clocks: 94fe8b45aaSThierry Reding items: 95fe8b45aaSThierry Reding - description: display core clock 96fe8b45aaSThierry Reding - description: display hub clock 97fe8b45aaSThierry Reding 98fe8b45aaSThierry Reding clock-names: 99fe8b45aaSThierry Reding items: 100fe8b45aaSThierry Reding - const: disp 101fe8b45aaSThierry Reding - const: hub 102fe8b45aaSThierry Reding 103fe8b45aaSThierry RedingadditionalProperties: false 104fe8b45aaSThierry Reding 105fe8b45aaSThierry Redingrequired: 106fe8b45aaSThierry Reding - compatible 107fe8b45aaSThierry Reding - reg 108fe8b45aaSThierry Reding - clocks 109fe8b45aaSThierry Reding - clock-names 110fe8b45aaSThierry Reding - resets 111fe8b45aaSThierry Reding - reset-names 112fe8b45aaSThierry Reding - power-domains 113fe8b45aaSThierry Reding - "#address-cells" 114fe8b45aaSThierry Reding - "#size-cells" 115fe8b45aaSThierry Reding - ranges 116fe8b45aaSThierry Reding 117fe8b45aaSThierry Redingexamples: 118fe8b45aaSThierry Reding - | 119fe8b45aaSThierry Reding #include <dt-bindings/clock/tegra186-clock.h> 120fe8b45aaSThierry Reding #include <dt-bindings/interrupt-controller/arm-gic.h> 121fe8b45aaSThierry Reding #include <dt-bindings/memory/tegra186-mc.h> 122fe8b45aaSThierry Reding #include <dt-bindings/power/tegra186-powergate.h> 123fe8b45aaSThierry Reding #include <dt-bindings/reset/tegra186-reset.h> 124fe8b45aaSThierry Reding 125fe8b45aaSThierry Reding display-hub@15200000 { 126fe8b45aaSThierry Reding compatible = "nvidia,tegra186-display"; 127fe8b45aaSThierry Reding reg = <0x15200000 0x00040000>; 128fe8b45aaSThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 129fe8b45aaSThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 130fe8b45aaSThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 131fe8b45aaSThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 132fe8b45aaSThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 133fe8b45aaSThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 134fe8b45aaSThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 135fe8b45aaSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 136fe8b45aaSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 137fe8b45aaSThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 138fe8b45aaSThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 139fe8b45aaSThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 140fe8b45aaSThierry Reding clock-names = "disp", "dsc", "hub"; 141fe8b45aaSThierry Reding 142fe8b45aaSThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 143fe8b45aaSThierry Reding 144fe8b45aaSThierry Reding #address-cells = <1>; 145fe8b45aaSThierry Reding #size-cells = <1>; 146fe8b45aaSThierry Reding 147fe8b45aaSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 148fe8b45aaSThierry Reding 149fe8b45aaSThierry Reding display@15200000 { 150fe8b45aaSThierry Reding compatible = "nvidia,tegra186-dc"; 151fe8b45aaSThierry Reding reg = <0x15200000 0x10000>; 152fe8b45aaSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 153fe8b45aaSThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 154fe8b45aaSThierry Reding clock-names = "dc"; 155fe8b45aaSThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 156fe8b45aaSThierry Reding reset-names = "dc"; 157fe8b45aaSThierry Reding 158fe8b45aaSThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 159fe8b45aaSThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 160fe8b45aaSThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 161fe8b45aaSThierry Reding interconnect-names = "dma-mem", "read-1"; 162fe8b45aaSThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 163fe8b45aaSThierry Reding 164fe8b45aaSThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 165fe8b45aaSThierry Reding nvidia,head = <0>; 166fe8b45aaSThierry Reding }; 167fe8b45aaSThierry Reding 168fe8b45aaSThierry Reding display@15210000 { 169fe8b45aaSThierry Reding compatible = "nvidia,tegra186-dc"; 170fe8b45aaSThierry Reding reg = <0x15210000 0x10000>; 171fe8b45aaSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 172fe8b45aaSThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 173fe8b45aaSThierry Reding clock-names = "dc"; 174fe8b45aaSThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 175fe8b45aaSThierry Reding reset-names = "dc"; 176fe8b45aaSThierry Reding 177fe8b45aaSThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 178fe8b45aaSThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 179fe8b45aaSThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 180fe8b45aaSThierry Reding interconnect-names = "dma-mem", "read-1"; 181fe8b45aaSThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 182fe8b45aaSThierry Reding 183fe8b45aaSThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 184fe8b45aaSThierry Reding nvidia,head = <1>; 185fe8b45aaSThierry Reding }; 186fe8b45aaSThierry Reding 187fe8b45aaSThierry Reding display@15220000 { 188fe8b45aaSThierry Reding compatible = "nvidia,tegra186-dc"; 189fe8b45aaSThierry Reding reg = <0x15220000 0x10000>; 190fe8b45aaSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 191fe8b45aaSThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 192fe8b45aaSThierry Reding clock-names = "dc"; 193fe8b45aaSThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 194fe8b45aaSThierry Reding reset-names = "dc"; 195fe8b45aaSThierry Reding 196fe8b45aaSThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 197fe8b45aaSThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 198fe8b45aaSThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 199fe8b45aaSThierry Reding interconnect-names = "dma-mem", "read-1"; 200fe8b45aaSThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 201fe8b45aaSThierry Reding 202fe8b45aaSThierry Reding nvidia,outputs = <&sor0 &sor1>; 203fe8b45aaSThierry Reding nvidia,head = <2>; 204fe8b45aaSThierry Reding }; 205fe8b45aaSThierry Reding }; 206fe8b45aaSThierry Reding 207fe8b45aaSThierry Reding - | 208fe8b45aaSThierry Reding #include <dt-bindings/clock/tegra194-clock.h> 209fe8b45aaSThierry Reding #include <dt-bindings/interrupt-controller/arm-gic.h> 210fe8b45aaSThierry Reding #include <dt-bindings/memory/tegra194-mc.h> 211fe8b45aaSThierry Reding #include <dt-bindings/power/tegra194-powergate.h> 212fe8b45aaSThierry Reding #include <dt-bindings/reset/tegra194-reset.h> 213fe8b45aaSThierry Reding 214fe8b45aaSThierry Reding display-hub@15200000 { 215fe8b45aaSThierry Reding compatible = "nvidia,tegra194-display"; 216fe8b45aaSThierry Reding reg = <0x15200000 0x00040000>; 217fe8b45aaSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 218fe8b45aaSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 219fe8b45aaSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 220fe8b45aaSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 221fe8b45aaSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 222fe8b45aaSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 223fe8b45aaSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 224fe8b45aaSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 225fe8b45aaSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 226fe8b45aaSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 227fe8b45aaSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 228fe8b45aaSThierry Reding clock-names = "disp", "hub"; 229fe8b45aaSThierry Reding 230fe8b45aaSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 231fe8b45aaSThierry Reding 232fe8b45aaSThierry Reding #address-cells = <1>; 233fe8b45aaSThierry Reding #size-cells = <1>; 234fe8b45aaSThierry Reding 235fe8b45aaSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 236fe8b45aaSThierry Reding 237fe8b45aaSThierry Reding display@15200000 { 238fe8b45aaSThierry Reding compatible = "nvidia,tegra194-dc"; 239fe8b45aaSThierry Reding reg = <0x15200000 0x10000>; 240fe8b45aaSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 241fe8b45aaSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 242fe8b45aaSThierry Reding clock-names = "dc"; 243fe8b45aaSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 244fe8b45aaSThierry Reding reset-names = "dc"; 245fe8b45aaSThierry Reding 246fe8b45aaSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 247fe8b45aaSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 248fe8b45aaSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 249fe8b45aaSThierry Reding interconnect-names = "dma-mem", "read-1"; 250fe8b45aaSThierry Reding 251fe8b45aaSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 252fe8b45aaSThierry Reding nvidia,head = <0>; 253fe8b45aaSThierry Reding }; 254fe8b45aaSThierry Reding 255fe8b45aaSThierry Reding display@15210000 { 256fe8b45aaSThierry Reding compatible = "nvidia,tegra194-dc"; 257fe8b45aaSThierry Reding reg = <0x15210000 0x10000>; 258fe8b45aaSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 259fe8b45aaSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 260fe8b45aaSThierry Reding clock-names = "dc"; 261fe8b45aaSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 262fe8b45aaSThierry Reding reset-names = "dc"; 263fe8b45aaSThierry Reding 264fe8b45aaSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 265fe8b45aaSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 266fe8b45aaSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 267fe8b45aaSThierry Reding interconnect-names = "dma-mem", "read-1"; 268fe8b45aaSThierry Reding 269fe8b45aaSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 270fe8b45aaSThierry Reding nvidia,head = <1>; 271fe8b45aaSThierry Reding }; 272fe8b45aaSThierry Reding 273fe8b45aaSThierry Reding display@15220000 { 274fe8b45aaSThierry Reding compatible = "nvidia,tegra194-dc"; 275fe8b45aaSThierry Reding reg = <0x15220000 0x10000>; 276fe8b45aaSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 277fe8b45aaSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 278fe8b45aaSThierry Reding clock-names = "dc"; 279fe8b45aaSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 280fe8b45aaSThierry Reding reset-names = "dc"; 281fe8b45aaSThierry Reding 282fe8b45aaSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 283fe8b45aaSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 284fe8b45aaSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 285fe8b45aaSThierry Reding interconnect-names = "dma-mem", "read-1"; 286fe8b45aaSThierry Reding 287fe8b45aaSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 288fe8b45aaSThierry Reding nvidia,head = <2>; 289fe8b45aaSThierry Reding }; 290fe8b45aaSThierry Reding 291fe8b45aaSThierry Reding display@15230000 { 292fe8b45aaSThierry Reding compatible = "nvidia,tegra194-dc"; 293fe8b45aaSThierry Reding reg = <0x15230000 0x10000>; 294fe8b45aaSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 295fe8b45aaSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 296fe8b45aaSThierry Reding clock-names = "dc"; 297fe8b45aaSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 298fe8b45aaSThierry Reding reset-names = "dc"; 299fe8b45aaSThierry Reding 300fe8b45aaSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 301fe8b45aaSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 302fe8b45aaSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 303fe8b45aaSThierry Reding interconnect-names = "dma-mem", "read-1"; 304fe8b45aaSThierry Reding 305fe8b45aaSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 306fe8b45aaSThierry Reding nvidia,head = <3>; 307fe8b45aaSThierry Reding }; 308fe8b45aaSThierry Reding }; 309