Lines Matching full:display
39 struct intel_display *display = to_intel_display(encoder); in intel_encoder_is_c10phy() local
48 if (display->platform.pantherlake && phy < PHY_C) in intel_encoder_is_c10phy()
51 if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C) in intel_encoder_is_c10phy()
75 * by display and lane 1 is owned by USB. in intel_cx0_get_owned_lane_mask()
82 assert_dc_off(struct intel_display *display) in assert_dc_off() argument
86 enabled = intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF); in assert_dc_off()
87 drm_WARN_ON(display->drm, !enabled); in assert_dc_off()
92 struct intel_display *display = to_intel_display(encoder); in intel_cx0_program_msgbus_timer() local
96 intel_de_rmw(display, in intel_cx0_program_msgbus_timer()
97 XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane), in intel_cx0_program_msgbus_timer()
113 struct intel_display *display = to_intel_display(encoder); in intel_cx0_phy_transaction_begin() local
118 wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF); in intel_cx0_phy_transaction_begin()
126 struct intel_display *display = to_intel_display(encoder); in intel_cx0_phy_transaction_end() local
130 intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref); in intel_cx0_phy_transaction_end()
136 struct intel_display *display = to_intel_display(encoder); in intel_clear_response_ready_flag() local
138 intel_de_rmw(display, in intel_clear_response_ready_flag()
139 XELPDP_PORT_P2M_MSGBUS_STATUS(display, encoder->port, lane), in intel_clear_response_ready_flag()
145 struct intel_display *display = to_intel_display(encoder); in intel_cx0_bus_reset() local
149 intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), in intel_cx0_bus_reset()
152 if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), in intel_cx0_bus_reset()
155 drm_err_once(display->drm, in intel_cx0_bus_reset()
167 struct intel_display *display = to_intel_display(encoder); in intel_cx0_wait_for_ack() local
171 if (intel_de_wait_custom(display, in intel_cx0_wait_for_ack()
172 XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane), in intel_cx0_wait_for_ack()
177 drm_dbg_kms(display->drm, in intel_cx0_wait_for_ack()
181 if (!(intel_de_read(display, XELPDP_PORT_MSGBUS_TIMER(display, port, lane)) & in intel_cx0_wait_for_ack()
183 drm_dbg_kms(display->drm, in intel_cx0_wait_for_ack()
192 drm_dbg_kms(display->drm, in intel_cx0_wait_for_ack()
201 drm_dbg_kms(display->drm, in intel_cx0_wait_for_ack()
215 struct intel_display *display = to_intel_display(encoder); in __intel_cx0_read_once() local
221 if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), in __intel_cx0_read_once()
224 drm_dbg_kms(display->drm, in __intel_cx0_read_once()
230 intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), in __intel_cx0_read_once()
246 if (DISPLAY_VER(display) < 30) in __intel_cx0_read_once()
255 struct intel_display *display = to_intel_display(encoder); in __intel_cx0_read() local
259 assert_dc_off(display); in __intel_cx0_read()
269 drm_err_once(display->drm, in __intel_cx0_read()
287 struct intel_display *display = to_intel_display(encoder); in __intel_cx0_write_once() local
293 if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), in __intel_cx0_write_once()
296 drm_dbg_kms(display->drm, in __intel_cx0_write_once()
302 intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), in __intel_cx0_write_once()
309 if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), in __intel_cx0_write_once()
312 drm_dbg_kms(display->drm, in __intel_cx0_write_once()
322 } else if ((intel_de_read(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane)) & in __intel_cx0_write_once()
324 drm_dbg_kms(display->drm, in __intel_cx0_write_once()
337 if (DISPLAY_VER(display) < 30) in __intel_cx0_write_once()
346 struct intel_display *display = to_intel_display(encoder); in __intel_cx0_write() local
350 assert_dc_off(display); in __intel_cx0_write()
360 drm_err_once(display->drm, in __intel_cx0_write()
376 struct intel_display *display = to_intel_display(encoder); in intel_c20_sram_write() local
378 assert_dc_off(display); in intel_c20_sram_write()
390 struct intel_display *display = to_intel_display(encoder); in intel_c20_sram_read() local
393 assert_dc_off(display); in intel_c20_sram_read()
457 struct intel_display *display = to_intel_display(encoder); in intel_cx0_phy_set_signal_levels() local
472 if (drm_WARN_ON_ONCE(display->drm, !trans)) { in intel_cx0_phy_set_signal_levels()
2034 struct intel_display *display = to_intel_display(encoder); in intel_cx0pll_update_ssc() local
2037 if (intel_panel_use_ssc(display)) { in intel_cx0pll_update_ssc()
2048 struct intel_display *display = to_intel_display(encoder); in intel_c10pll_update_pll() local
2054 drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 9); in intel_c10pll_update_pll()
2134 static void intel_c10_pll_program(struct intel_display *display, in intel_c10_pll_program() argument
2162 static void intel_c10pll_dump_hw_state(struct intel_display *display, in intel_c10pll_dump_hw_state() argument
2171 drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ", in intel_c10pll_dump_hw_state()
2178 drm_dbg_kms(display->drm, "quot: %u, rem: %u, den: %u,\n", in intel_c10pll_dump_hw_state()
2185 drm_dbg_kms(display->drm, in intel_c10pll_dump_hw_state()
2188 drm_dbg_kms(display->drm, "c10pll_rawhw_state:"); in intel_c10pll_dump_hw_state()
2189 drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, in intel_c10pll_dump_hw_state()
2194 drm_dbg_kms(display->drm, in intel_c10pll_dump_hw_state()
2217 struct intel_display *display = to_intel_display(crtc_state); in intel_c20_hdmi_tmds_tx_cgf_1() local
2222 if (DISPLAY_VER(display) >= 20) { in intel_c20_hdmi_tmds_tx_cgf_1()
2225 } else if (display->platform.battlemage) { in intel_c20_hdmi_tmds_tx_cgf_1()
2227 } else if (display->platform.meteorlake_u || in intel_c20_hdmi_tmds_tx_cgf_1()
2312 struct intel_display *display = to_intel_display(crtc_state); in intel_c20_pll_tables_get() local
2316 if (DISPLAY_RUNTIME_INFO(display)->edp_typec_support) in intel_c20_pll_tables_get()
2318 if (DISPLAY_VERx100(display) == 1401) in intel_c20_pll_tables_get()
2322 if (DISPLAY_VER(display) >= 30) in intel_c20_pll_tables_get()
2324 else if (DISPLAY_VERx100(display) == 1401) in intel_c20_pll_tables_get()
2428 struct intel_display *display = to_intel_display(encoder); in intel_c20pll_readout_hw_state() local
2443 PHY_C20_B_TX_CNTX_CFG(display, i)); in intel_c20pll_readout_hw_state()
2447 PHY_C20_A_TX_CNTX_CFG(display, i)); in intel_c20pll_readout_hw_state()
2455 PHY_C20_B_CMN_CNTX_CFG(display, i)); in intel_c20pll_readout_hw_state()
2459 PHY_C20_A_CMN_CNTX_CFG(display, i)); in intel_c20pll_readout_hw_state()
2468 PHY_C20_B_MPLLB_CNTX_CFG(display, i)); in intel_c20pll_readout_hw_state()
2472 PHY_C20_A_MPLLB_CNTX_CFG(display, i)); in intel_c20pll_readout_hw_state()
2480 PHY_C20_B_MPLLA_CNTX_CFG(display, i)); in intel_c20pll_readout_hw_state()
2484 PHY_C20_A_MPLLA_CNTX_CFG(display, i)); in intel_c20pll_readout_hw_state()
2493 static void intel_c20pll_dump_hw_state(struct intel_display *display, in intel_c20pll_dump_hw_state() argument
2498 drm_dbg_kms(display->drm, "c20pll_hw_state:\n"); in intel_c20pll_dump_hw_state()
2499 drm_dbg_kms(display->drm, in intel_c20pll_dump_hw_state()
2502 drm_dbg_kms(display->drm, in intel_c20pll_dump_hw_state()
2508 drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i, in intel_c20pll_dump_hw_state()
2512 drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i, in intel_c20pll_dump_hw_state()
2517 void intel_cx0pll_dump_hw_state(struct intel_display *display, in intel_cx0pll_dump_hw_state() argument
2521 intel_c10pll_dump_hw_state(display, &hw_state->c10); in intel_cx0pll_dump_hw_state()
2523 intel_c20pll_dump_hw_state(display, &hw_state->c20); in intel_cx0pll_dump_hw_state()
2623 static void intel_c20_pll_program(struct intel_display *display, in intel_c20_pll_program() argument
2651 PHY_C20_A_TX_CNTX_CFG(display, i), in intel_c20_pll_program()
2655 PHY_C20_B_TX_CNTX_CFG(display, i), in intel_c20_pll_program()
2663 PHY_C20_A_CMN_CNTX_CFG(display, i), in intel_c20_pll_program()
2667 PHY_C20_B_CMN_CNTX_CFG(display, i), in intel_c20_pll_program()
2676 PHY_C20_A_MPLLB_CNTX_CFG(display, i), in intel_c20_pll_program()
2680 PHY_C20_B_MPLLB_CNTX_CFG(display, i), in intel_c20_pll_program()
2687 PHY_C20_A_MPLLA_CNTX_CFG(display, i), in intel_c20_pll_program()
2691 PHY_C20_B_MPLLA_CNTX_CFG(display, i), in intel_c20_pll_program()
2759 struct intel_display *display = to_intel_display(encoder); in intel_program_port_clock_ctl() local
2762 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), in intel_program_port_clock_ctl()
2772 val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK); in intel_program_port_clock_ctl()
2774 val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK); in intel_program_port_clock_ctl()
2783 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), in intel_program_port_clock_ctl()
2785 XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA | in intel_program_port_clock_ctl()
2814 struct intel_display *display = to_intel_display(encoder); in intel_cx0_powerdown_change_sequence() local
2817 i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port); in intel_cx0_powerdown_change_sequence()
2820 intel_de_rmw(display, buf_ctl2_reg, in intel_cx0_powerdown_change_sequence()
2826 if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), in intel_cx0_powerdown_change_sequence()
2829 drm_dbg_kms(display->drm, in intel_cx0_powerdown_change_sequence()
2835 intel_de_rmw(display, buf_ctl2_reg, in intel_cx0_powerdown_change_sequence()
2840 if (intel_de_wait_custom(display, buf_ctl2_reg, in intel_cx0_powerdown_change_sequence()
2843 drm_warn(display->drm, in intel_cx0_powerdown_change_sequence()
2850 struct intel_display *display = to_intel_display(encoder); in intel_cx0_setup_powerdown() local
2853 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), in intel_cx0_setup_powerdown()
2856 intel_de_rmw(display, XELPDP_PORT_BUF_CTL3(display, port), in intel_cx0_setup_powerdown()
2888 struct intel_display *display = to_intel_display(encoder); in intel_cx0_phy_lane_reset() local
2901 if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL1(display, port), in intel_cx0_phy_lane_reset()
2905 drm_warn(display->drm, in intel_cx0_phy_lane_reset()
2909 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, in intel_cx0_phy_lane_reset()
2912 if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port), in intel_cx0_phy_lane_reset()
2915 drm_warn(display->drm, in intel_cx0_phy_lane_reset()
2919 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port), in intel_cx0_phy_lane_reset()
2923 if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port), in intel_cx0_phy_lane_reset()
2927 drm_warn(display->drm, in intel_cx0_phy_lane_reset()
2935 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 0); in intel_cx0_phy_lane_reset()
2937 if (intel_de_wait_for_clear(display, XELPDP_PORT_BUF_CTL2(display, port), in intel_cx0_phy_lane_reset()
2940 drm_warn(display->drm, in intel_cx0_phy_lane_reset()
3015 struct intel_display *display = to_intel_display(encoder); in __intel_cx0pll_enable() local
3047 intel_c10_pll_program(display, encoder, &pll_state->c10); in __intel_cx0pll_enable()
3049 intel_c20_pll_program(display, encoder, &pll_state->c20, is_dp, port_clock); in __intel_cx0pll_enable()
3058 * 7. Follow the Display Voltage Frequency Switching - Sequence in __intel_cx0pll_enable()
3066 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock); in __intel_cx0pll_enable()
3072 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), in __intel_cx0pll_enable()
3077 if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), in __intel_cx0pll_enable()
3081 drm_warn(display->drm, "Port %c PLL not locked after %dus.\n", in __intel_cx0pll_enable()
3085 * 11. Follow the Display Voltage Frequency Switching Sequence After in __intel_cx0pll_enable()
3103 struct intel_display *display = to_intel_display(encoder); in intel_mtl_tbt_calc_port_clock() local
3106 val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)); in intel_mtl_tbt_calc_port_clock()
3108 clock = XELPDP_DDI_CLOCK_SELECT_GET(display, val); in intel_mtl_tbt_calc_port_clock()
3110 drm_WARN_ON(display->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE)); in intel_mtl_tbt_calc_port_clock()
3111 drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_REQUEST)); in intel_mtl_tbt_calc_port_clock()
3112 drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_ACK)); in intel_mtl_tbt_calc_port_clock()
3133 static int intel_mtl_tbt_clock_select(struct intel_display *display, in intel_mtl_tbt_clock_select() argument
3146 if (DISPLAY_VER(display) < 30) { in intel_mtl_tbt_clock_select()
3147 drm_WARN_ON(display->drm, "UHBR10 not supported for the platform\n"); in intel_mtl_tbt_clock_select()
3152 if (DISPLAY_VER(display) < 30) { in intel_mtl_tbt_clock_select()
3153 drm_WARN_ON(display->drm, "UHBR20 not supported for the platform\n"); in intel_mtl_tbt_clock_select()
3166 struct intel_display *display = to_intel_display(encoder); in intel_mtl_tbt_pll_enable() local
3176 mask = XELPDP_DDI_CLOCK_SELECT_MASK(display); in intel_mtl_tbt_pll_enable()
3177 val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, in intel_mtl_tbt_pll_enable()
3178 intel_mtl_tbt_clock_select(display, crtc_state->port_clock)); in intel_mtl_tbt_pll_enable()
3183 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), in intel_mtl_tbt_pll_enable()
3187 val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)); in intel_mtl_tbt_pll_enable()
3190 * 3. Follow the Display Voltage Frequency Switching - Sequence in intel_mtl_tbt_pll_enable()
3198 intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val); in intel_mtl_tbt_pll_enable()
3201 if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), in intel_mtl_tbt_pll_enable()
3205 drm_warn(display->drm, in intel_mtl_tbt_pll_enable()
3210 * 6. Follow the Display Voltage Frequency Switching Sequence After in intel_mtl_tbt_pll_enable()
3218 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), in intel_mtl_tbt_pll_enable()
3241 struct intel_display *display = to_intel_display(encoder); in intel_lnl_mac_transmit_lfps() local
3246 if (DISPLAY_VER(display) < 20 || in intel_lnl_mac_transmit_lfps()
3275 struct intel_display *display = to_intel_display(encoder); in cx0_power_control_disable_val() local
3280 if ((display->platform.battlemage && encoder->port == PORT_A) || in cx0_power_control_disable_val()
3281 (DISPLAY_VER(display) >= 30 && encoder->type == INTEL_OUTPUT_EDP)) in cx0_power_control_disable_val()
3289 struct intel_display *display = to_intel_display(encoder); in intel_cx0pll_disable() local
3298 * 2. Follow the Display Voltage Frequency Switching Sequence Before in intel_cx0pll_disable()
3306 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), in intel_cx0pll_disable()
3311 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0); in intel_cx0pll_disable()
3316 if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), in intel_cx0pll_disable()
3320 drm_warn(display->drm, in intel_cx0pll_disable()
3325 * 6. Follow the Display Voltage Frequency Switching Sequence After in intel_cx0pll_disable()
3330 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), in intel_cx0pll_disable()
3331 XELPDP_DDI_CLOCK_SELECT_MASK(display), 0); in intel_cx0pll_disable()
3332 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), in intel_cx0pll_disable()
3340 struct intel_display *display = to_intel_display(encoder); in intel_cx0_pll_is_enabled() local
3344 return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) & in intel_cx0_pll_is_enabled()
3350 struct intel_display *display = to_intel_display(encoder); in intel_mtl_tbt_pll_disable() local
3354 * 1. Follow the Display Voltage Frequency Switching Sequence Before in intel_mtl_tbt_pll_disable()
3361 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), in intel_mtl_tbt_pll_disable()
3365 if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), in intel_mtl_tbt_pll_disable()
3367 drm_warn(display->drm, in intel_mtl_tbt_pll_disable()
3372 * 4. Follow the Display Voltage Frequency Switching Sequence After in intel_mtl_tbt_pll_disable()
3379 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), in intel_mtl_tbt_pll_disable()
3380 XELPDP_DDI_CLOCK_SELECT_MASK(display) | in intel_mtl_tbt_pll_disable()
3384 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0); in intel_mtl_tbt_pll_disable()
3401 struct intel_display *display = to_intel_display(encoder); in intel_mtl_port_pll_type() local
3408 val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)); in intel_mtl_port_pll_type()
3409 clock = XELPDP_DDI_CLOCK_SELECT_GET(display, val); in intel_mtl_port_pll_type()
3423 struct intel_display *display = to_intel_display(state); in intel_c10pll_state_verify() local
3430 INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->pll[i] != expected, in intel_c10pll_state_verify()
3436 INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->tx != mpllb_sw_state->tx, in intel_c10pll_state_verify()
3441 INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->cmn != mpllb_sw_state->cmn, in intel_c10pll_state_verify()
3530 struct intel_display *display = to_intel_display(state); in intel_c20pll_state_verify() local
3537 INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->clock != clock, in intel_c20pll_state_verify()
3542 INTEL_DISPLAY_STATE_WARN(display, sw_use_mpllb != hw_use_mpllb, in intel_c20pll_state_verify()
3549 INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i], in intel_c20pll_state_verify()
3556 INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i], in intel_c20pll_state_verify()
3564 INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->tx[i] != mpll_sw_state->tx[i], in intel_c20pll_state_verify()
3571 INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i], in intel_c20pll_state_verify()
3581 struct intel_display *display = to_intel_display(state); in intel_cx0pll_state_verify() local
3587 if (DISPLAY_VER(display) < 14) in intel_cx0pll_state_verify()
3612 * The dedicated display PHYs reset to a power state that blocks S0ix, increasing idle
3623 void intel_cx0_pll_power_save_wa(struct intel_display *display) in intel_cx0_pll_power_save_wa() argument
3627 if (DISPLAY_VER(display) != 30) in intel_cx0_pll_power_save_wa()
3630 for_each_intel_encoder(display->drm, encoder) { in intel_cx0_pll_power_save_wa()
3647 drm_WARN_ON(display->drm, in intel_cx0_pll_power_save_wa()
3652 drm_dbg_kms(display->drm, in intel_cx0_pll_power_save_wa()