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/freebsd/contrib/wpa/src/common/
H A Dieee802_11_defs.h3 * Copyright (c) 2002-2019, Jouni Malinen <j@w1.fi>
4 * Copyright (c) 2007-2008 Intel Corporation
39 #define WLAN_GET_SEQ_FRAG(seq) ((seq) & (BIT(3) | BIT(2) | BIT(1) | BIT(0)))
41 (((seq) & (~(BIT(3) | BIT(2) | BIT(1) | BIT(0)))) >> 4)
54 #define WLAN_FC_STYPE_PROBE_RESP 5
77 #define WLAN_FC_STYPE_CFACK 5
98 #define WLAN_AUTH_FILS_SK_PFS 5
105 #define WLAN_CAPABILITY_ESS BIT(0)
106 #define WLAN_CAPABILITY_IBSS BIT(1)
107 #define WLAN_CAPABILITY_CF_POLLABLE BIT(2)
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/freebsd/sys/dev/dpaa2/
H A Ddpaa2_ni_dpkg.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause
4 * Copyright © 2013-2015 Freescale Semiconductor, Inc.
41 * Copyright © 2021-2022 Dmitry Salychev
68 #define BIT(x) (1ul << (x)) macro
71 * DPKG_NUM_OF_MASKS - Number of masks per key extraction
76 * DPKG_MAX_NUM_OF_EXTRACTS - Number of extractions per key profile
81 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
93 * enum dpkg_extract_type - Enumeration for selecting extraction type
96 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td1 //===- ARCInstrFormats.td - ARC Instruction Formats --------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
21 "\n return isUInt<"#BSz#">(N->getSExtValue());"> {
27 "\n return isInt<"#BSz#">(N->getSExtValue());"> {
31 // e.g. s3 field may encode the signed integers values -1 .. 6
34 "\n return isInt<"#BSz#">(N->getSExtValue());"> {
64 class ExtMode<bit mode, string instSfx, string asmSfx> {
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/freebsd/sys/contrib/dev/rtw89/
H A Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
20 #define DATA_RATE_NSS_MASK_V1 GENMASK(7, 5)
28 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
41 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_ht_mcs()
49 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_mcs()
62 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_nss()
71 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
72 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
73 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
76 #define RTW89_TXWD_BODY0_STF_MODE BIT(10)
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H A Dpci.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
16 #define OOBS_SEN_MASK GENMASK(5, 1)
18 #define BAC_OOBS_SEL BIT(4)
20 #define B_BAC_EQ_SEL BIT(5)
22 #define MANUAL_LVL_MASK GENMASK(8, 5)
24 #define B_PCIE_BIT_PSAVE BIT(15)
26 #define OFFSET_CAL_MODE BIT(13)
27 #define BAC_RX_TEST_EN BIT(6)
32 #define B_PCIE_BIT_PINOUT_DIS BIT(3)
37 #define B_PCIE_BIT_RD_SEL BIT(2)
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H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_SOP_ASWRM BIT(31)
23 #define B_AX_SOP_PWMM_DSWR BIT(29)
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/freebsd/sys/contrib/dev/rtw88/
H A Drtw8821c.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
21 -20, -24, -28, -31, -34, -37, -40, -44};
26 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8821ce_efuse_parsing()
32 ether_addr_copy(efuse->addr, map->u.mac_addr); in rtw8821cu_efuse_parsing()
38 ether_addr_copy(efuse->addr, map->s.mac_addr); in rtw8821cs_efuse_parsing()
50 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_read_efuse()
51 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_read_efuse()
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H A Drtw8822b.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
26 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8822be_efuse_parsing()
32 ether_addr_copy(efuse->addr, map->u.mac_addr); in rtw8822bu_efuse_parsing()
38 ether_addr_copy(efuse->addr, map->s.mac_addr); in rtw8822bs_efuse_parsing()
43 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8822b_read_efuse()
49 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(7)); in rtw8822b_read_efuse()
50 efuse->rfe_option = map->rfe_option; in rtw8822b_read_efuse()
51 efuse->rf_board_option = map->rf_board_option; in rtw8822b_read_efuse()
52 efuse->crystal_cap = map->xtal_k; in rtw8822b_read_efuse()
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H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
9 #define BIT_FEN_EN_25_1 BIT(13)
10 #define BIT_FEN_ELDR BIT(12)
11 #define BIT_FEN_PCIEA BIT(6)
12 #define BIT_FEN_CPUEN BIT(2)
13 #define BIT_FEN_USBA BIT(2)
14 #define BIT_FEN_BB_GLB_RST BIT(1)
15 #define BIT_FEN_BB_RSTB BIT(0)
16 #define BIT_R_DIS_PRST BIT(6)
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/freebsd/crypto/openssl/test/recipes/
H A D20-test_dhparam.t2 # Copyright 2020-2025 The OpenSSL Project Authors. All Rights Reserved.
26 my $fipsconf = srctop_file("test", "fips-and-base.cnf");
31 my $gen = shift; #2, 5 or something else (0 is "something else")?
40 if (-T $file) {
45 if ($firstline eq "-----BEGIN DH PARAMETERS-----") {
47 } elsif ($firstline eq "-----BEGIN X9.42 DH PARAMETERS-----") {
63 my @textdata = run(app(['openssl', 'dhparam', '-in', $file, '-noout',
64 '-text', '-inform', $format]), capture => 1);
76 if (defined $textdata[0] && $textdata[0] =~ /DH Parameters: \((\d+) bit\)/) {
80 if ($gen == 2 || $gen == 5) {
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsV.td1 //===-- RISCVInstrFormatsV.td - RISC-V V Instruction Formats -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V V extension instruction formats.
11 //===----------------------------------------------------------------------===//
38 class RISCVLSUMOP<bits<5> val> {
39 bits<5> Value = val;
59 bits<5> uimm;
60 bits<5> rd;
65 let Inst{29-20} = vtypei{9-0};
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/freebsd/sys/dev/clk/rockchip/
H A Drk3328_cru.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2018-2021 Emmanuel Vadot <manu@freebsd.org>
61 #define PLL_NPLL 5
256 /* Bit 3 bus_src_clk_en */
257 /* Bit 4 clk_ddrphy_src_en */
258 /* Bit 5 clk_ddrpd_src_en */
259 /* Bit 6 clk_ddrmon_en */
260 /* Bit 7-8 unused */
261 /* Bit 9 testclk_en */
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrFormats.td1 //===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
15 // ad-hoc solution used to emit machine instruction encodings by our machine
27 def DPSoRegRegFrm : Format<5>;
76 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
78 class UnaryDP { bit isUnaryDataProc = 1; }
80 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
81 // a 16-bit Thumb instruction if certain conditions are met.
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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
46 #define MT_TX_FREE_PAIR BIT(31)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
58 #define MT_TXD1_AMSDU BIT(23)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
67 #define MT_TXD2_FIX_RATE BIT(31)
68 #define MT_TXD2_FIXED_RATE BIT(30)
72 #define MT_TXD2_HTC_VLD BIT(13)
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H A Dmt76x02_regs.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
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H A Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
38 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
39 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
40 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
41 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
42 #define MT_RXD1_NORMAL_GROUP_5 BIT(20)
44 #define MT_RXD1_NORMAL_CM BIT(23)
45 #define MT_RXD1_NORMAL_CLM BIT(24)
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/freebsd/sys/dev/ixgbe/
H A Dixgbe_type_e610.h2 SPDX-License-Identifier: BSD-3-Clause
40 #ifndef BIT
41 #define BIT(a) (1UL << (a)) macro
42 #endif /* !BIT */
50 #define DIVIDE_AND_ROUND_UP(a, b) (((a) + (b) - 1) / (b))
55 * ROUND_UP - round up to next arbitrary multiple (not a power of 2)
77 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
80 (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
97 * ixgbe_struct_size - size of struct with C99 flexible array member
103 (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num))
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td1 //===- AArch64InstrFormats.td - AArch64 Instruction Formats --*- tblgen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
14 // ad-hoc solution used to emit machine instruction encodings by our machine
35 def DestructiveBinary : DestructiveInstTypeEnum<5>;
56 def SMEMatrixTileQ : SMEMatrixTypeEnum<5>;
63 // If a bit is set, then if the corresponding bit in the
68 // as to make it more obvious what it means in ARM-land.
75 bit isWhile = 0;
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/freebsd/contrib/netbsd-tests/include/
H A Dd_bitstring_8.out10 5 0 32 1
15 be: 0 -1 00000000
16 is: 0 -1 00000000
33 5 0
38 be: 0 -1 00000000
39 is: 0 -1 00000000
46 be: 0 -1 00000000
47 is: 0 -1 00000000
50 be: 0 -1 00000000
51 is: 0 -1 00000000
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/freebsd/sys/dev/flash/flexspi/
H A Dflex_spi.h1 /*-
29 #define BIT(x) (1 << (x)) macro
35 #define FSPI_MCR0_LEARN_EN BIT(15)
36 #define FSPI_MCR0_SCRFRUN_EN BIT(14)
37 #define FSPI_MCR0_OCTCOMB_EN BIT(13)
38 #define FSPI_MCR0_DOZE_EN BIT(12)
39 #define FSPI_MCR0_HSEN BIT(11)
40 #define FSPI_MCR0_SERCLKDIV BIT(8)
41 #define FSPI_MCR0_ATDF_EN BIT(7)
42 #define FSPI_MCR0_ARDF_EN BIT(6)
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/freebsd/sys/dev/sfxge/common/
H A Defx_regs.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
48 * FR_AB_EE_VPD_CFG0_REG_SF(128bit):
54 * FR_AB_EE_VPD_CFG0_REG(128bit):
81 #define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5
82 #define FRF_AB_EE_VPD_ACCESS_ON_LBN 5
94 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit):
100 * FR_AB_PCIE_SD_CTL0123_REG(128bit):
162 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit):
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/freebsd/lib/libpmc/pmu-events/arch/x86/cascadelakex/
H A Dfloating-point.json3 …"BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision float…
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …-bit packed computational double precision floating-point instructions retired; some instructions …
13 …"BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision float…
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
18 …-bit packed computational single precision floating-point instructions retired; some instructions …
23 …"BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision float…
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
28 …-bit packed double computational precision floating-point instructions retired; some instructions …
33 …"BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision float…
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
35 #define MT_HW_INFO_BASE ((dev)->reg_map[MT_HW_BASE])
40 #define MT_TOP_3NSS BIT(24)
45 #define MT_TOP_MISC2 ((dev)->reg_map[MT_TOP_CFG_BASE] + 0x134)
49 #define MT_TOP_MISC2_FW_PWR_ON BIT(1)
59 #define MT_MCU_PCIE_REMAP_2 ((dev)->reg_map[MT_PCIE_REMAP_2])
62 #define MT_PCIE_REMAP_BASE_2 ((dev)->reg_map[MT_PCIE_REMAP_BASE2])
69 #define MT_HIF(ofs) ((dev)->reg_map[MT_HIF_BASE] + (ofs))
71 #define MT_HIF_LOGIC_RST_N BIT(4)
74 #define MT_PDMA_AXI_SLPPROT_ENABLE BIT(0)
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
38 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
40 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
54 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
55 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
56 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
57 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
78 …Bit 0 - For ending "endless completion". 0 - When receiving a completion timeout while receiving a…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 … // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo push overflow…
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