Lines Matching +full:5 +full:- +full:bit
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2018-2021 Emmanuel Vadot <manu@freebsd.org>
61 #define PLL_NPLL 5
256 /* Bit 3 bus_src_clk_en */
257 /* Bit 4 clk_ddrphy_src_en */
258 /* Bit 5 clk_ddrpd_src_en */
259 /* Bit 6 clk_ddrmon_en */
260 /* Bit 7-8 unused */
261 /* Bit 9 testclk_en */
265 /* Bit 13-15 unused */
268 /* Bit 0 unused */
273 GATE(0, "clk_i2s1_frac", "clk_i2s1_frac_f", 1, 5),
291 GATE(SCLK_TSP, "clk_tsp", "clk_tsp_c", 2, 5),
307 /* Bit 3 gmac_gpll_src_en Unused ? */
308 /* Bit 4 gmac_vpll_src_en Unused ? */
309 GATE(SCLK_MAC2IO_OUT, "clk_mac2io_out", "clk_mac2io_out_c", 3, 5),
310 /* Bit 6-7 unused */
312 /* Bit 9-15 unused */
320 GATE(SCLK_EMMC, "clk_emmc_src", "clk_emmc_c", 4, 5),
324 /* Bit 9 clk_usb3phy_ref_25m_en */
326 /* Bit 11-15 unused */
329 GATE(ACLK_RGA_PRE, "aclk_rga_pre", "aclk_rga_pre_c", 5, 0),
330 GATE(SCLK_RGA, "sclk_rga", "sclk_rga_c", 5, 0),
331 GATE(ACLK_VIO_PRE, "aclk_vio_pre", "aclk_vio_pre_c", 5, 2),
332 GATE(SCLK_CIF_OUT, "clk_cif_src", "clk_cif_src_c", 5, 3),
333 GATE(SCLK_HDMI_SFC, "clk_hdmi_sfc", "xin24m", 5, 4),
334 GATE(ACLK_VOP_PRE, "aclk_vop_pre", "aclk_vop_pre_c", 5, 5),
335 GATE(DCLK_LCDC_SRC, "vop_dclk_src", "vop_dclk_src_c", 5, 6),
336 /* Bit 7-15 unused */
344 GATE(ACLK_VPU_PRE, "aclk_vpu_pre", "aclk_vpu_pre_c", 6, 5),
347 /* Bit 8-15 unused */
350 /* Bit 0 aclk_core_en */
351 /* Bit 1 clk_core_periph_en */
352 /* Bit 2 clk_jtag_en */
353 /* Bit 3 unused */
354 /* Bit 4 pclk_ddr_en */
355 /* Bit 5-15 unused */
363 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 8, 5),
369 /* Bit 11-15 unused */
377 GATE(SCLK_MAC2IO_TX, "clk_gmac2io_tx", "clk_mac2io", 9, 5),
380 /* Bit 8-15 unused */
386 /* Bit 3-15 unused */
390 /* Bit 1-3 unused */
392 /* Bit 5-7 unused */
394 /* Bit 9-15 unused */
400 /* Bit 0 aclk_core_niu_en */
401 /* Bit 1 aclk_gic400_en */
402 /* Bit 2-15 unused */
407 /* Bit 2-15 unused */
410 /* Bit 0 aclk_intmem_en Unused */
411 /* Bit 1 aclk_dmac_bus_en Unused */
412 /* Bit 2 hclk_rom_en Unused */
415 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 15, 5),
426 /* Bit 15 pclk_phy_niu_en */
434 GATE(PCLK_SPI, "pclk_spi", "pclk_bus", 16, 5),
448 /* Bit 1 unused */
452 GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy", 17, 5),
456 /* Bit 9 unused */
460 /* Bit 13 clk_hsadc_0_tsp_en Depend on a gpio clock ? */
465 /* Bit 0 unused */
466 /* Bit 1 pclk_ddr_upctl_en */
467 /* Bit 2 pclk_ddr_msch_en */
468 /* Bit 3 pclk_ddr_mon_en */
469 /* Bit 4 aclk_ddr_upctl_en */
470 /* Bit 5 clk_ddr_upctl_en */
471 /* Bit 6 clk_ddr_msch_en */
472 /* Bit 7 pclk_ddrstdby_en */
473 /* Bit 8-15 unused */
479 /* Bit 3-5 unused */
484 /* Bit 10 unused */
495 /* Bit 0-1 unused */
499 GATE(0, "hclk_vop_niu", "hclk_vio_pre", 21, 5),
517 GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 22, 5),
518 /* Bit 6-15 unused */
525 /* Bit 4-15 unused */
532 /* Bit 4-15 unused */
540 GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 25, 5),
542 /* Bit 7-15 unused */
550 GATE(0, "pclk_gmac_niu", "pclk_gmac", 26, 5),
551 /* Bit 6-15 unused */
554 /* Bit 0 clk_ddrphy_en */
555 /* Bit 1 clk4x_ddrphy_en */
563 /* Bit 5-15 unused */
634 PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066329),
805 .div_width = 5,
859 COMP(0, "aclk_bus_pre_c", pll_src_cpll_gpll_hdmiphy_p, 0, 0, 8, 5, 13, 2),
879 COMP(0, "clk_efuse_c", pll_src_cpll_gpll_xin24m_p, 0, 5, 8, 5, 14, 2),
937 COMP(0, "clk_pdm_c", pll_src_cpll_gpll_apll_p, 0, 20, 8, 5, 14, 2),
938 COMP(0, "clk_crypto_c", pll_src_cpll_gpll_p, 0, 20, 0, 5, 7, 1),
941 COMP(0, "clk_tsp_c", pll_src_cpll_gpll_p, 0, 21, 8, 5, 15, 1),
954 COMP(0, "aclk_gmac_c", pll_src_cpll_gpll_p, 0, 35, 0, 5, 6, 2),
959 COMP(0, "clk_mac2phy_src_c", pll_src_cpll_gpll_p, 0, 26, 0, 5, 7, 1),
962 COMP(0, "clk_mac2io_src_c", pll_src_cpll_gpll_p, 0, 27, 0, 5, 7, 1),
963 COMP(0, "clk_mac2io_out_c", pll_src_cpll_gpll_p, 0, 27, 8, 5, 15, 1),
966 COMP(ACLK_PERI_PRE, "aclk_peri_pre", pll_src_cpll_gpll_hdmiphy_p, 0, 28, 0, 5, 6, 2),
993 COMP(0, "aclk_rga_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 36, 8, 5, 14, 2),
994 COMP(0, "sclk_rga_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 36, 0, 5, 6, 2),
997 COMP(0, "aclk_vio_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 37, 0, 5, 6, 2),
998 CDIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_vio_pre", 0, 37, 8, 5),
1004 COMP(0, "aclk_vop_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 39, 0, 5, 6, 2),
1017 COMP(0, "clk_cif_src_c", mux_cif_p, 0, 42, 0, 5, 5, 1),
1023 COMP(0, "aclk_gpu_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 44, 0, 5, 6, 2),
1036 COMP(0, "sclk_cabac_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 48, 8, 5, 14, 2),
1037 COMP(0, "aclk_rkvdec_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 48, 0, 5, 6, 2),
1040 COMP(0, "sclk_vdec_core_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 49, 0, 5, 6, 2),
1043 COMP(0, "aclk_vpu_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 50, 0, 5, 6, 2),
1046 COMP(0, "sclk_venc_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 51, 8, 5, 14, 2),
1047 COMP(0, "aclk_rkvenc_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 51, 0, 5, 6, 2),
1050 COMP(0, "sclk_venc_dsp_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 51, 8, 5, 14, 2),
1075 if (ofw_bus_is_compatible(dev, "rockchip,rk3328-cru")) { in rk3328_cru_probe()
1089 sc->dev = dev; in rk3328_cru_attach()
1091 sc->gates = rk3328_gates; in rk3328_cru_attach()
1092 sc->ngates = nitems(rk3328_gates); in rk3328_cru_attach()
1094 sc->clks = rk3328_clks; in rk3328_cru_attach()
1095 sc->nclks = nitems(rk3328_clks); in rk3328_cru_attach()
1097 sc->reset_offset = 0x300; in rk3328_cru_attach()
1098 sc->reset_num = 184; in rk3328_cru_attach()