Lines Matching +full:5 +full:- +full:bit
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
48 * FR_AB_EE_VPD_CFG0_REG_SF(128bit):
54 * FR_AB_EE_VPD_CFG0_REG(128bit):
81 #define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5
82 #define FRF_AB_EE_VPD_ACCESS_ON_LBN 5
94 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit):
100 * FR_AB_PCIE_SD_CTL0123_REG(128bit):
162 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit):
163 * PCIE SerDes control register 4 and 5
168 * FR_AB_PCIE_SD_CTL45_REG(128bit):
169 * PCIE SerDes control register 4 and 5
208 * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit):
214 * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit):
248 * FR_AB_HW_INIT_REG_SF(128bit):
254 * FR_AZ_HW_INIT_REG(128bit):
285 #define FRF_AB_INTB_VEC_WIDTH 5
287 #define FRF_AB_INTA_VEC_WIDTH 5
290 #define FRF_AZ_US_DISABLE_LBN 5
302 * FR_AB_NIC_STAT_REG_SF(128bit):
308 * FR_AB_NIC_STAT_REG(128bit):
334 * FR_AB_GLB_CTL_REG_SF(128bit):
340 * FR_AB_GLB_CTL_REG(128bit):
422 #define FFE_AB_EXT_PHY_RST_DUR_2560US 5
432 * FR_AZ_IOM_IND_ADR_REG(32bit):
433 * IO-mapped indirect access address register
444 * FR_AZ_IOM_IND_DAT_REG(32bit):
445 * IO-mapped indirect access data register
454 * FR_AZ_ADR_REGION_REG(128bit):
470 * FR_AZ_INT_EN_REG_KER(128bit):
486 * FR_AZ_INT_EN_REG_CHAR(128bit):
502 * FR_AZ_INT_ADR_REG_KER(128bit):
518 * FR_AZ_INT_ADR_REG_CHAR(128bit):
534 * FR_AA_INT_ACK_KER(32bit):
544 * FR_BZ_INT_ISR0_REG(128bit):
558 * FR_AB_EE_SPI_HCMD_REG(128bit):
571 #define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5
582 * FR_CZ_USR_EV_CFG(32bit):
594 * FR_AB_EE_SPI_HADR_REG(128bit):
606 * FR_AB_EE_SPI_HDATA_REG(128bit):
622 * FR_AB_EE_BASE_PAGE_REG(128bit):
634 * FR_AB_EE_VPD_SW_CNTL_REG(128bit):
648 * FR_AB_EE_VPD_SW_DATA_REG(128bit):
658 * FR_BB_PCIE_CORE_INDIRECT_REG(64bit):
672 * FR_AB_GPIO_CTL_REG(128bit):
782 #define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5
796 * FR_AZ_FATAL_INTR_REG_KER(128bit):
846 #define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5
860 * FR_AZ_FATAL_INTR_REG_CHAR(128bit):
910 #define FRF_AZ_RDESCQ_OWN_INT_CHAR_LBN 5
924 * FR_AZ_DP_CTRL_REG(128bit):
934 * FR_AZ_MEM_STAT_REG(128bit):
962 * FR_PORT0_CS_DEBUG_REG(128bit):
980 #define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5
984 #define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5
992 #define FRF_AB_EM_DEBUG_ADDR_WIDTH 5
994 #define FRF_AB_SR_DEBUG_ADDR_WIDTH 5
996 #define FRF_AB_EV_DEBUG_ADDR_WIDTH 5
998 #define FRF_AB_RX_DEBUG_ADDR_WIDTH 5
1000 #define FRF_AB_TX_DEBUG_ADDR_WIDTH 5
1002 #define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5
1007 * FR_AZ_DRIVER_REG(128bit):
1008 * Driver scratch register [0-7]
1019 * FR_AZ_ALTERA_BUILD_REG(128bit):
1029 * FR_AZ_CSR_SPARE_REG(128bit):
1047 * FR_BZ_DEBUG_DATA_OUT_REG(128bit):
1059 * FR_BZ_EVQ_RPTR_REGP0(32bit):
1067 * FR_AA_EVQ_RPTR_REG_KER(32bit):
1075 * FR_AZ_EVQ_RPTR_REG(32bit):
1084 * FR_BB_EVQ_RPTR_REGP123(32bit):
1098 * FR_BZ_TIMER_COMMAND_REGP0(128bit):
1106 * FR_AA_TIMER_COMMAND_REG_KER(128bit):
1114 * FR_AB_TIMER_COMMAND_REGP123(128bit):
1122 * FR_AA_TIMER_COMMAND_REGP0(128bit):
1140 * FR_AZ_DRV_EV_REG(128bit):
1156 * FR_AZ_EVQ_CTL_REG(128bit):
1174 * FR_AZ_EVQ_CNT1_REG(128bit):
1196 * FR_AZ_EVQ_CNT2_REG(128bit):
1218 * FR_CZ_USR_EV_REG(32bit):
1230 * FR_AZ_BUF_TBL_CFG_REG(128bit):
1240 * FR_AZ_SRM_RX_DC_CFG_REG(128bit):
1252 * FR_AZ_SRM_TX_DC_CFG_REG(128bit):
1262 * FR_AZ_SRM_CFG_REG(128bit):
1268 * FR_AZ_SRM_CFG_REG(128bit):
1274 #define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5
1286 * FR_AZ_BUF_TBL_UPD_REG(128bit):
1302 * FR_AZ_SRM_UPD_EVQ_REG(128bit):
1312 * FR_AZ_SRAM_PARITY_REG(128bit):
1330 * FR_AZ_RX_CFG_REG(128bit):
1363 #define FRF_BZ_RX_XON_TX_TH_WIDTH 5
1371 #define FRF_BZ_RX_XOFF_TX_TH_WIDTH 5
1375 #define FRF_AA_RX_XON_TX_TH_WIDTH 5
1379 #define FRF_AA_RX_XOFF_TX_TH_WIDTH 5
1385 #define FRF_AA_RX_XON_MAC_TH_WIDTH 5
1389 #define FRF_AA_RX_XOFF_MAC_TH_WIDTH 5
1394 * FR_AZ_RX_FILTER_CTL_REG(128bit):
1434 * FR_AZ_RX_FLUSH_DESCQ_REG(128bit):
1446 * FR_BZ_RX_DESC_UPD_REGP0(128bit):
1454 * FR_AA_RX_DESC_UPD_REG_KER(128bit):
1462 * FR_AB_RX_DESC_UPD_REGP123(128bit):
1470 * FR_AA_RX_DESC_UPD_REGP0(128bit):
1490 * FR_AZ_RX_DC_CFG_REG(128bit):
1506 * FR_AZ_RX_DC_PF_WM_REG(128bit):
1507 * Receive descriptor cache pre-fetch watermark register
1518 * FR_BZ_RX_RSS_TKEY_REG(128bit):
1536 * FR_AZ_RX_NODESC_DROP_REG(128bit):
1546 * FR_AZ_RX_SELF_RST_REG(128bit):
1564 * FR_AZ_RX_DEBUG_REG(128bit):
1578 * FR_AZ_RX_PUSH_DROP_REG(128bit):
1588 * FR_CZ_RX_RSS_IPV6_REG1(128bit):
1606 * FR_CZ_RX_RSS_IPV6_REG2(128bit):
1624 * FR_CZ_RX_RSS_IPV6_REG3(128bit):
1644 * FR_AZ_TX_FLUSH_DESCQ_REG(128bit):
1656 * FR_BZ_TX_DESC_UPD_REGP0(128bit):
1664 * FR_AA_TX_DESC_UPD_REG_KER(128bit):
1672 * FR_AB_TX_DESC_UPD_REGP123(128bit):
1680 * FR_AA_TX_DESC_UPD_REGP0(128bit):
1702 * FR_AZ_TX_DC_CFG_REG(128bit):
1715 * FR_AA_TX_CHKSM_CFG_REG(128bit):
1731 * FR_AZ_TX_CFG_REG(128bit):
1761 #define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5
1773 * FR_AZ_TX_PUSH_DROP_REG(128bit):
1783 * FR_AZ_TX_RESERVED_REG(128bit):
1816 #define FRF_AZ_TX_XP_TIMER_WIDTH 5
1853 * FR_BZ_TX_PACE_REG(128bit):
1859 * FR_AA_TX_PACE_REG(128bit):
1869 #define FRF_AZ_TX_PACE_FB_BASE_LBN 5
1872 #define FRF_AZ_TX_PACE_BIN_TH_WIDTH 5
1875 * FR_AZ_TX_PACE_DROP_QID_REG(128bit):
1885 * FR_AB_TX_VLAN_REG(128bit):
1943 * FR_AZ_TX_IPFIL_PORTEN_REG(128bit):
2017 * FR_AB_TX_IPFIL_TBL(128bit):
2035 * FR_AB_MD_TXD_REG(128bit):
2045 * FR_AB_MD_RXD_REG(128bit):
2055 * FR_AB_MD_CS_REG(128bit):
2071 #define FRF_AB_MD_INT_CLR_LBN 5
2085 * FR_AB_MD_PHY_ADR_REG(128bit):
2095 * FR_AB_MD_ID_REG(128bit):
2102 #define FRF_AB_MD_PRT_ADR_WIDTH 5
2104 #define FRF_AB_MD_DEV_ADR_WIDTH 5
2107 * FR_AB_MD_STAT_REG(128bit):
2125 * FR_AB_MAC_STAT_DMA_REG(128bit):
2141 * FR_AB_MAC_CTRL_REG(128bit):
2151 #define FRF_AB_MAC_XG_DISTXCRC_LBN 5
2167 * FR_BB_GEN_MODE_REG(128bit):
2183 * FR_AB_MAC_MC_HASH_REG0(128bit):
2201 * FR_AB_MAC_MC_HASH_REG1(128bit):
2219 * FR_AB_GM_CFG1_REG(32bit):
2239 #define FRF_AB_GM_RX_FC_EN_LBN 5
2253 * FR_AB_GM_CFG2_REG(32bit):
2265 #define FRF_AB_GM_HUGE_FRM_EN_LBN 5
2277 * FR_AB_GM_IPG_REG(32bit):
2293 * FR_AB_GM_HD_REG(32bit):
2315 * FR_AB_GM_MAX_FLEN_REG(32bit):
2325 * FR_AB_GM_TEST_REG(32bit):
2341 * FR_AB_GM_ADR1_REG(32bit):
2357 * FR_AB_GM_ADR2_REG(32bit):
2369 * FR_AB_GMF_CFG0_REG(32bit):
2407 * FR_AB_GMF_CFG1_REG(32bit):
2414 #define FRF_AB_GMF_CFGFRTH_WIDTH 5
2419 * FR_AB_GMF_CFG2_REG(32bit):
2431 * FR_AB_GMF_CFG3_REG(32bit):
2443 * FR_AB_GMF_CFG4_REG(32bit):
2453 * FR_AB_GMF_CFG5_REG(32bit):
2454 * GMAC FIFO configuration register 5
2473 * FR_BB_TX_SRC_MAC_TBL(128bit):
2495 * FR_BB_TX_SRC_MAC_CTL_REG(128bit):
2511 * FR_AB_XM_ADR_LO_REG(128bit):
2521 * FR_AB_XM_ADR_HI_REG(128bit):
2531 * FR_AB_XM_GLB_CFG_REG(128bit):
2547 #define FRF_AB_XM_WAN_MODE_LBN 5
2555 * FR_AB_XM_TX_CFG_REG(128bit):
2571 #define FRF_AB_XM_AUTO_PAD_LBN 5
2581 * FR_AB_XM_RX_CFG_REG(128bit):
2611 * FR_AB_XM_MGT_INT_MASK(128bit):
2631 * FR_AB_XM_FC_REG(128bit):
2647 #define FRF_AB_XM_REJ_CNTL_MCAST_LBN 5
2657 * FR_AB_XM_PAUSE_TIME_REG(128bit):
2669 * FR_AB_XM_TX_PARAM_REG(128bit):
2685 * FR_AB_XM_RX_PARAM_REG(128bit):
2697 * FR_AB_XM_MGT_INT_MSK_REG(128bit):
2715 * FR_AB_XX_PWR_RST_REG(128bit):
2765 #define FRF_AB_XX_RESETB_EN_LBN 5
2777 * FR_AB_XX_SD_CTL_REG(128bit):
2813 * FR_AB_XX_TXDRV_CTL_REG(128bit):
2837 * FR_AB_XX_PRBS_CTL_REG(128bit):
2881 #define FRF_AB_XX_CH1_TX_PRBS_INV_LBN 5
2893 * FR_AB_XX_PRBS_CHK_REG(128bit):
2921 #define FRF_AB_XX_CH1_PRBS_FRUN_LBN 5
2935 * FR_AB_XX_PRBS_ERR_REG(128bit):
2951 * FR_AB_XX_CORE_STAT_REG(128bit):
3009 #define FRF_AB_XX_CHAR_ERR_CH1_LBN 5
3023 * FR_AA_RX_DESC_PTR_TBL_KER(128bit):
3031 * FR_AZ_RX_DESC_PTR_TBL(128bit):
3062 #define FRF_AZ_RX_DESCQ_LABEL_LBN 5
3063 #define FRF_AZ_RX_DESCQ_LABEL_WIDTH 5
3078 * FR_AA_TX_DESC_PTR_TBL_KER(128bit):
3086 * FR_AZ_TX_DESC_PTR_TBL(128bit):
3125 #define FRF_AZ_TX_DESCQ_LABEL_LBN 5
3126 #define FRF_AZ_TX_DESCQ_LABEL_WIDTH 5
3139 * FR_AA_EVQ_PTR_TBL_KER(128bit):
3147 * FR_AZ_EVQ_PTR_TBL(128bit):
3167 #define FFE_AZ_EVQ_SIZE_16K 5
3177 * FR_AA_BUF_HALF_TBL_KER(64bit):
3185 * FR_AZ_BUF_HALF_TBL(64bit):
3204 * FR_AA_BUF_FULL_TBL_KER(64bit):
3212 * FR_AZ_BUF_FULL_TBL(64bit):
3242 * FR_AZ_RX_FILTER_TBL0(128bit):
3250 * FR_AB_RX_FILTER_TBL1(128bit):
3276 * FR_CZ_RX_MAC_FILTER_TBL0(128bit):
3304 * FR_AZ_TIMER_TBL(128bit):
3341 * FR_BZ_TX_PACE_TBL(128bit):
3350 * FR_AA_TX_PACE_TBL(128bit):
3359 #define FRF_AZ_TX_PACE_WIDTH 5
3362 * FR_BZ_RX_INDIRECTION_TBL(7bit):
3374 * FR_CZ_TX_FILTER_TBL0(128bit):
3396 * FR_CZ_TX_MAC_FILTER_TBL0(128bit):
3418 * FR_CZ_MC_TREG_SMEM(32bit):
3430 * FR_BB_MSIX_VECTOR_TABLE(128bit):
3438 * FR_CZ_MSIX_VECTOR_TABLE(128bit):
3458 * FR_BB_MSIX_PBA_TABLE(32bit):
3459 * MSIX Pending Bit Array
3466 * FR_CZ_MSIX_PBA_TABLE(32bit):
3467 * MSIX Pending Bit Array
3478 * FR_AZ_SRM_DBG_REG(64bit):
3496 * FR_AA_INT_ACK_CHAR(32bit):
3514 #define FSE_AZ_SRM_UPD_DONE_EV 5
3528 #define FSE_AZ_EV_CODE_DRIVER_EV 5
3575 #define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5
3599 #define FSF_AZ_RX_EV_Q_LABEL_WIDTH 5
3641 #define FSF_AZ_TX_EV_Q_LABEL_WIDTH 5
3698 /* Sub-fields of an RX flush completion event */
3706 * Falcon non-volatile configuration