Lines Matching +full:5 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
26 ether_addr_copy(efuse->addr, map->e.mac_addr);
32 ether_addr_copy(efuse->addr, map->u.mac_addr);
38 ether_addr_copy(efuse->addr, map->s.mac_addr);
43 struct rtw_efuse *efuse = &rtwdev->efuse;
49 efuse->rfe_option = map->rfe_option;
50 efuse->rf_board_option = map->rf_board_option;
51 efuse->crystal_cap = map->xtal_k;
52 efuse->pa_type_2g = map->pa_type;
53 efuse->pa_type_5g = map->pa_type;
54 efuse->lna_type_2g = map->lna_type_2g[0];
55 efuse->lna_type_5g = map->lna_type_5g[0];
56 efuse->channel_plan = map->channel_plan;
57 efuse->country_code[0] = map->country_code[0];
58 efuse->country_code[1] = map->country_code[1];
59 efuse->bt_setting = map->rf_bt_setting;
60 efuse->regd = map->rf_board_option & 0x7;
61 efuse->thermal_meter[RF_PATH_A] = map->thermal_meter;
62 efuse->thermal_meter_k = map->thermal_meter;
65 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
79 return -ENOTSUPP;
88 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3);
89 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0);
90 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1);
94 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3);
98 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3);
126 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
131 dm_info->default_ofdm_index = 24;
133 dm_info->default_ofdm_index = swing_idx;
135 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
136 ewma_thermal_init(&dm_info->avg_thermal[path]);
137 dm_info->delta_power_index[path] = 0;
139 dm_info->pwr_trk_triggered = false;
140 dm_info->pwr_trk_init_trigger = true;
141 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
153 struct rtw_hal *hal = &rtwdev->hal;
169 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
177 rtw8822b_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
267 /* Set beacon cotnrol - enable TSF and other related functions */
291 struct rtw_hal *hal = &rtwdev->hal;
296 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0);
300 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0);
303 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0);
305 if (hal->antenna_rx == BB_PATH_AB ||
306 hal->antenna_tx == BB_PATH_AB) {
309 } else if (hal->antenna_rx == hal->antenna_tx) {
320 struct rtw_hal *hal = &rtwdev->hal;
332 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0);
335 if (hal->antenna_rx == BB_PATH_AB ||
336 hal->antenna_tx == BB_PATH_AB) {
339 } else if (hal->antenna_rx == hal->antenna_tx) {
386 *reg82c = cca_ccut->reg82c[col];
387 *reg830 = cca_ccut->reg830[col];
388 *reg838 = cca_ccut->reg838[col];
417 [5] = IFEM_EXT_CCUT(ifem),
423 struct rtw_hal *hal = &rtwdev->hal;
424 struct rtw_efuse *efuse = &rtwdev->efuse;
431 cca_ccut = rfe_info->cca_ccut_2g;
433 if (hal->antenna_rx == BB_PATH_A ||
434 hal->antenna_rx == BB_PATH_B)
439 cca_ccut = rfe_info->cca_ccut_5g;
441 if (hal->antenna_rx == BB_PATH_A ||
442 hal->antenna_rx == BB_PATH_B)
450 switch (rfe_info->fem) {
454 if (rfe_info->ifem_ext)
469 if ((hal->cut_version == RTW_CHIP_VER_CUT_B &&
474 (efuse->rfe_option == 5 && col == CCUT_IDX_2R_5G))
482 if (is_efem_cca && !(hal->cut_version == RTW_CHIP_VER_CUT_B))
499 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
501 #define RF18_BAND_5G (BIT(16) | BIT(8))
503 #define RF18_RFSI_MASK (BIT(18) | BIT(17))
504 #define RF18_RFSI_GE_CH80 (BIT(17))
505 #define RF18_RFSI_GT_CH144 (BIT(18))
506 #define RF18_BW_MASK (BIT(11) | BIT(10))
507 #define RF18_BW_20M (BIT(11) | BIT(10))
508 #define RF18_BW_40M (BIT(11))
509 #define RF18_BW_80M (BIT(10))
510 #define RFBE_MASK (BIT(17) | BIT(16) | BIT(15))
512 struct rtw_hal *hal = &rtwdev->hal;
545 rf_reg_be = low_band[(channel - 36) >> 1];
547 rf_reg_be = middle_band[(channel - 100) >> 1];
549 rf_reg_be = high_band[(channel - 149) >> 1];
557 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1);
559 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0);
562 if (hal->rf_type > RF_1T1R)
565 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
566 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
576 struct rtw_hal *hal = &rtwdev->hal;
580 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2);
582 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2);
587 hal->antenna_rx | (hal->antenna_rx << 4));
594 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1);
595 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0);
596 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
599 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
600 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
601 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
604 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
605 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
606 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
613 struct rtw_efuse *efuse = &rtwdev->efuse;
614 u8 rfe_option = efuse->rfe_option;
618 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
619 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
620 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
635 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
636 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
637 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
667 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
671 rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
673 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
680 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
688 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
692 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1);
698 val32 |= ((BIT(6) | RTW_CHANNEL_WIDTH_20));
701 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
702 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
707 val32 |= ((BIT(7) | RTW_CHANNEL_WIDTH_20));
710 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
711 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
719 struct rtw_efuse *efuse = &rtwdev->efuse;
722 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info),
723 "rfe_option %d is out of boundary\n", efuse->rfe_option))
726 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option];
734 (*rfe_info->rtw_set_channel_rfe)(rtwdev, channel);
740 struct rtw_efuse *efuse = &rtwdev->efuse;
742 u8 ch = rtwdev->hal.current_channel;
746 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info),
747 "rfe_option %d is out of boundary\n", efuse->rfe_option))
750 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option];
762 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3);
763 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1);
764 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1);
783 if (is_tx2_path || rtwdev->mp_mode) {
789 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0);
790 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0);
801 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0);
802 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0);
803 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0);
805 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1);
806 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1);
807 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1);
810 for (counter = 100; counter > 0; counter--) {
835 (*rfe_info->rtw_set_channel_rfe)(rtwdev, ch);
841 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
842 s8 min_rx_power = -120;
846 pkt_stat->rx_power[RF_PATH_A] = pwdb - 110;
847 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
848 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
849 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
851 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
857 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
859 s8 min_rx_power = -120;
865 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
879 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
880 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110;
881 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2);
882 pkt_stat->bw = bw;
883 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
884 pkt_stat->rx_power[RF_PATH_B],
887 dm_info->curr_rx_rate = pkt_stat->rate;
889 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status);
890 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status);
892 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status);
893 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status);
895 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status);
896 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status);
898 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
899 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
900 dm_info->rssi[path] = rssi;
901 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1;
902 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1;
904 rx_evm = pkt_stat->rx_evm[path];
910 evm_dbm = ((u8)-rx_evm >> 1);
912 dm_info->rx_evm_dbm[path] = evm_dbm;
941 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
946 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
947 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
948 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
949 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) &&
951 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
952 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
953 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
954 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
955 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
956 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
957 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
958 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
960 /* drv_info_sz is in unit of 8-bytes */
961 pkt_stat->drv_info_sz *= 8;
964 if (pkt_stat->is_c2h)
967 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
968 pkt_stat->drv_info_sz);
969 if (pkt_stat->phy_status) {
970 phy_status = rx_desc + desc_sz + pkt_stat->shift;
980 struct rtw_hal *hal = &rtwdev->hal;
988 pwr_index = hal->tx_pwr_tbl[path][rate];
1002 struct rtw_hal *hal = &rtwdev->hal;
1005 for (path = 0; path < hal->rf_path_num; path++) {
1027 struct rtw_hal *hal = &rtwdev->hal;
1034 return -EINVAL;
1039 return -EINVAL;
1042 hal->antenna_tx = antenna_tx;
1043 hal->antenna_rx = antenna_rx;
1061 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1068 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28);
1072 dm_info->cck_fa_cnt = cck_fa_cnt;
1073 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
1074 dm_info->total_fa_cnt = ofdm_fa_cnt;
1075 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
1078 dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
1079 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1081 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
1082 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1084 dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
1085 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1087 dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
1088 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1091 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16);
1092 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
1095 dm_info->cck_cca_cnt = cca32_cnt & 0xffff;
1096 dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
1099 rtw_write32_set(rtwdev, 0x9a4, BIT(17));
1100 rtw_write32_clr(rtwdev, 0x9a4, BIT(17));
1101 rtw_write32_clr(rtwdev, 0xa2c, BIT(15));
1102 rtw_write32_set(rtwdev, 0xa2c, BIT(15));
1103 rtw_write32_set(rtwdev, 0xb58, BIT(0));
1104 rtw_write32_clr(rtwdev, 0xb58, BIT(0));
1125 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
1143 /* 0x790[5:0]=0x5 */
1149 /* enable PTA (3-wire function form BT side) */
1164 struct rtw_coex *coex = &rtwdev->coex;
1165 struct rtw_coex_dm *coex_dm = &coex->dm;
1166 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1170 if (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status)
1173 coex_dm->cur_switch_status = (ctrl_type << 8) + pos_type;
1175 if (coex_rfe->ant_switch_diversity &&
1179 polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
1192 if (coex_rfe->rfe_module_type != 0x4 &&
1193 coex_rfe->rfe_module_type != 0x2)
1260 struct rtw_coex *coex = &rtwdev->coex;
1261 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1262 struct rtw_efuse *efuse = &rtwdev->efuse;
1265 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
1266 coex_rfe->ant_switch_polarity = 0;
1267 coex_rfe->ant_switch_diversity = false;
1268 if (coex_rfe->rfe_module_type == 0x12 ||
1269 coex_rfe->rfe_module_type == 0x15 ||
1270 coex_rfe->rfe_module_type == 0x16)
1271 coex_rfe->ant_switch_exist = false;
1273 coex_rfe->ant_switch_exist = true;
1275 if (coex_rfe->rfe_module_type == 2 ||
1276 coex_rfe->rfe_module_type == 4) {
1283 coex_rfe->wlg_at_btg = false;
1285 if (efuse->share_ant &&
1286 coex_rfe->ant_switch_exist && !is_ext_fem)
1287 coex_rfe->ant_switch_with_bt = true;
1289 coex_rfe->ant_switch_with_bt = false;
1308 struct rtw_coex *coex = &rtwdev->coex;
1309 struct rtw_coex_dm *coex_dm = &coex->dm;
1314 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
1317 coex_dm->cur_wl_pwr_lvl = wl_pwr;
1319 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power))
1320 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1;
1322 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl];
1330 struct rtw_coex *coex = &rtwdev->coex;
1331 struct rtw_coex_dm *coex_dm = &coex->dm;
1359 if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
1362 coex_dm->cur_wl_rx_low_gain_en = low_gain;
1364 if (coex_dm->cur_wl_rx_low_gain_en) {
1365 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n");
1375 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n");
1391 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1392 s8 delta_pwr_idx = dm_info->delta_power_index[path];
1393 u8 swing_upper_bound = dm_info->default_ofdm_index + 10;
1397 u8 swing_index = dm_info->default_ofdm_index;
1404 swing_index = dm_info->default_ofdm_index;
1407 swing_index = dm_info->default_ofdm_index +
1408 delta_pwr_idx - tx_pwr_idx_offset;
1412 if (dm_info->default_ofdm_index > abs(delta_pwr_idx))
1414 dm_info->default_ofdm_index + delta_pwr_idx;
1424 swing_index = RTW_TXSCALE_SIZE - 1;
1456 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1458 u8 channel = rtwdev->hal.current_channel;
1459 u8 band_width = rtwdev->hal.current_band_width;
1461 u8 tx_rate = dm_info->tx_rate;
1462 u8 max_pwr_idx = rtwdev->chip->max_power_index;
1469 pwr_idx_offset = max_pwr_idx - tx_pwr_idx;
1478 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1485 power_idx_last = dm_info->delta_power_index[path];
1493 dm_info->delta_power_index[path] = power_idx_cur;
1499 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1505 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff)
1512 if (dm_info->pwr_trk_init_trigger)
1513 dm_info->pwr_trk_init_trigger = false;
1518 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
1528 struct rtw_efuse *efuse = &rtwdev->efuse;
1529 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1531 if (efuse->power_track_type != 0)
1534 if (!dm_info->pwr_trk_triggered) {
1537 dm_info->pwr_trk_triggered = true;
1542 dm_info->pwr_trk_triggered = false;
1568 if (bfee->role == RTW_BFEE_SU)
1570 else if (bfee->role == RTW_BFEE_MU)
1593 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1597 igi = dm_info->igi_history[0];
1598 if (dm_info->edcca_mode == RTW_EDCCA_NORMAL) {
1600 h2l = l2h - EDCCA_L2H_H2L_DIFF_NORMAL;
1602 l2h = min_t(s8, igi, dm_info->l2h_th_ini);
1603 h2l = l2h - EDCCA_L2H_H2L_DIFF;
1623 RTW_PWR_CMD_WRITE, BIT(0), 0},
1628 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1633 RTW_PWR_CMD_WRITE, BIT(0), 0},
1638 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1661 RTW_PWR_CMD_WRITE, BIT(1), 0},
1666 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1671 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1681 RTW_PWR_CMD_WRITE, BIT(5), 0},
1686 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1691 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1696 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1701 RTW_PWR_CMD_WRITE, BIT(0), 0},
1711 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1716 RTW_PWR_CMD_WRITE, BIT(7), 0},
1721 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1726 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1731 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1736 RTW_PWR_CMD_POLLING, BIT(0), 0},
1741 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1761 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1771 RTW_PWR_CMD_WRITE, BIT(2), 0},
1776 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1781 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1794 RTW_PWR_CMD_WRITE, BIT(2), 0},
1799 RTW_PWR_CMD_WRITE, BIT(3), 0},
1819 RTW_PWR_CMD_WRITE, BIT(1), 0},
1824 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1829 RTW_PWR_CMD_WRITE, BIT(1), 0},
1834 RTW_PWR_CMD_WRITE, BIT(0), 0},
1839 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1844 RTW_PWR_CMD_POLLING, BIT(1), 0},
1849 RTW_PWR_CMD_WRITE, BIT(3), 0},
1854 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1867 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1877 RTW_PWR_CMD_WRITE, BIT(5), 0},
1882 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1887 RTW_PWR_CMD_WRITE, BIT(0), 0},
1892 RTW_PWR_CMD_WRITE, BIT(5), 0},
1897 RTW_PWR_CMD_WRITE, BIT(4), 0},
1902 RTW_PWR_CMD_WRITE, BIT(0), 0},
1907 RTW_PWR_CMD_WRITE, BIT(1), 0},
1912 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1917 RTW_PWR_CMD_WRITE, BIT(2), 0},
1922 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1927 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1932 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1937 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1942 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1947 RTW_PWR_CMD_POLLING, BIT(1), 0},
1952 RTW_PWR_CMD_WRITE, BIT(1), 0},
2118 [5] = RTW_DEF_RFE(8822b, 5, 5),
2204 /* Shared-Antenna Coex Table */
2206 {0xffffffff, 0xffffffff}, /* case-0 */
2211 {0xfafafafa, 0xfafafafa}, /* case-5 */
2216 {0x66555555, 0x6a5a5a5a}, /* case-10 */
2221 {0x66555555, 0xaaaaaaaa}, /* case-15 */
2226 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
2231 {0xffffffff, 0x6a5a5aaa}, /* case-25 */
2236 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
2241 /* Non-Shared-Antenna Coex Table */
2243 {0xffffffff, 0xffffffff}, /* case-100 */
2248 {0xfafafafa, 0xfafafafa}, /* case-105 */
2253 {0x66555555, 0x6a5a5a5a}, /* case-110 */
2258 {0xffff55ff, 0xffff55ff}, /* case-115 */
2263 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
2269 /* Shared-Antenna TDMA */
2271 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
2276 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
2281 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
2286 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
2291 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
2296 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
2301 /* Non-Shared-Antenna TDMA */
2303 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
2304 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
2308 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
2313 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
2318 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
2323 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
2327 /* rssi in percentage % (dbm = % - 100) */
2334 {0, 16, false, 7}, /* for WL-CPT */
2343 {0, 16, false, 7}, /* for WL-CPT */
2379 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2382 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2385 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2392 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2395 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2398 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2405 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2408 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2411 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2418 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2421 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2424 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2431 4, 5, 5, 5, 6, 6, 7, 7, 7, 8,
2437 5, 5, 6, 6, 6, 7, 7, 8, 8, 9,
2443 4, 5, 5, 5, 6, 6, 7, 7, 7, 8,
2448 0, 1, 1, 2, 2, 3, 3, 4, 4, 5,
2449 5, 6, 6, 7, 7, 8, 8, 9, 9, 10,
2455 4, 5, 5, 5, 6, 6, 7, 7, 7, 8,
2461 5, 5, 6, 6, 6, 7, 7, 8, 8, 9,
2467 4, 5, 5, 5, 6, 6, 7, 7, 7, 8,
2472 0, 1, 1, 2, 2, 3, 3, 4, 4, 5,
2473 5, 6, 6, 7, 7, 8, 8, 9, 9, 10,
2506 {0xcbd, BIT(0), RTW_REG_DOMAIN_MAC8},
2512 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2515 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
2516 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
2517 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2518 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2523 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2558 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),
2584 .l2h_th_ini_ad = -14 + EDCCA_IGI_BASE,