Lines Matching +full:5 +full:- +full:bit

3 …"BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision float…
5         "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …-bit packed computational double precision floating-point instructions retired; some instructions …
13 …"BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision float…
15         "CounterHTOff": "0,1,2,3,4,5,6,7",
18 …-bit packed computational single precision floating-point instructions retired; some instructions …
23 …"BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision float…
25         "CounterHTOff": "0,1,2,3,4,5,6,7",
28 …-bit packed double computational precision floating-point instructions retired; some instructions …
33 …"BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision float…
35         "CounterHTOff": "0,1,2,3,4,5,6,7",
38 …-bit packed single computational precision floating-point instructions retired; some instructions …
43 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
45         "CounterHTOff": "0,1,2,3,4,5,6,7",
48 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
53 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
55         "CounterHTOff": "0,1,2,3,4,5,6,7",
58 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
63 …": "Counts once for most SIMD scalar computational double precision floating-point instructions re…
65         "CounterHTOff": "0,1,2,3,4,5,6,7",
68 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
73 …": "Counts once for most SIMD scalar computational single precision floating-point instructions re…
75         "CounterHTOff": "0,1,2,3,4,5,6,7",
78 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
83 …   "BriefDescription": "Intel AVX-512 computational 512-bit packed BFloat16 instructions retired.",
85         "CounterHTOff": "0,1,2,3,4,5,6,7",
88 …ublicDescription": "Counts once for each Intel AVX-512 computational 512-bit packed BFloat16 float…
93 …   "BriefDescription": "Intel AVX-512 computational 128-bit packed BFloat16 instructions retired.",
95         "CounterHTOff": "0,1,2,3,4,5,6,7",
98 …ublicDescription": "Counts once for each Intel AVX-512 computational 128-bit packed BFloat16 float…
103 …   "BriefDescription": "Intel AVX-512 computational 256-bit packed BFloat16 instructions retired.",
105         "CounterHTOff": "0,1,2,3,4,5,6,7",
108 …ublicDescription": "Counts once for each Intel AVX-512 computational 256-bit packed BFloat16 float…
115         "CounterHTOff": "0,1,2,3,4,5,6,7",