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/freebsd/sys/dev/dpaa2/
H A Ddpaa2_ni_dpkg.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause
4 * Copyright © 2013-2015 Freescale Semiconductor, Inc.
13 * 2. Redistributions in binary form must reproduce the above copyright
41 * Copyright © 2021-2022 Dmitry Salychev
48 * 2. Redistributions in binary form must reproduce the above copyright
68 #define BIT(x) (1ul << (x)) macro
71 * DPKG_NUM_OF_MASKS - Number of masks per key extraction
76 * DPKG_MAX_NUM_OF_EXTRACTS - Number of extractions per key profile
81 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
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/freebsd/contrib/file/magic/Magdir/
H A Dispell2 #------------------------------------------------------------------------------
15 >0 byte 2 3.1 hash file,
17 >2 leshort 0x00 8-bit, no capitalization, 26 flags
18 >2 leshort 0x01 7-bit, no capitalization, 26 flags
19 >2 leshort 0x02 8-bit, capitalization, 26 flags
20 >2 leshort 0x03 7-bit, capitalization, 26 flags
21 >2 leshort 0x04 8-bit, no capitalization, 52 flags
22 >2 leshort 0x05 7-bit, no capitalization, 52 flags
23 >2 leshort 0x06 8-bit, capitalization, 52 flags
24 >2 leshort 0x07 7-bit, capitalization, 52 flags
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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Davxvnniint16intrin.h1 /*===----------- avxvnniint16intrin.h - AVXVNNIINT16 intrinsics-------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
26 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
27 /// corresponding unsigned 16-bit integers in \a __B, producing 2 intermediate
28 /// signed 16-bit results. Sum these 2 results with the corresponding
29 /// 32-bit integer in \a __W, and store the packed 32-bit results in \a dst.
40 /// A 128-bit vector of [4 x int].
42 /// A 128-bit vector of [8 x short].
44 /// A 128-bit vector of [8 x unsigned short].
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H A Demmintrin.h1 /*===---- emmintrin.h - SSE2 intrinsics ------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
54 __target__("sse2,no-evex512"), __min_vector_width__(128)))
57 __target__("mmx,sse2,no-evex512"), __min_vector_width__(64)))
59 /// Adds lower double-precision values in both operands and returns the
61 /// are copied from the upper double-precision value of the first operand.
68 /// A 128-bit vector of [2 x double] containing one of the source operands.
70 /// A 128-bit vector of [2 x double] containing one of the source operands.
71 /// \returns A 128-bit vector of [2 x double] whose lower 64 bits contain the
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H A Dmmintrin.h1 /*===---- mmintrin.h - MMX intrinsics --------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
26 __attribute__((__always_inline__, __nodebug__, __target__("mmx,no-evex512"), \
37 __target__("mmx,no-evex512")))
42 /// Constructs a 64-bit integer vector, setting the lower 32 bits to the
43 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
50 /// A 32-bit integer value.
51 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
59 /// Returns the lower 32 bits of a 64-bit integer vector as a 32-bit
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H A Dfmaintrin.h1 /*===---- fmaintrin.h - FMA intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
21 /// Computes a multiply-add of 128-bit vectors of [4 x float].
29 /// A 128-bit vector of [4 x float] containing the multiplicand.
31 /// A 128-bit vector of [4 x float] containing the multiplier.
33 /// A 128-bit vector of [4 x float] containing the addend.
34 /// \returns A 128-bit vector of [4 x float] containing the result.
41 /// Computes a multiply-add of 128-bit vectors of [2 x double].
49 /// A 128-bit vector of [2 x double] containing the multiplicand.
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H A Dsmmintrin.h1 /*===---- smmintrin.h - SSE4 intrinsics ------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
22 __target__("sse4.1,no-evex512"), __min_vector_width__(128)))
41 /// Rounds up each element of the 128-bit vector of [4 x float] to an
42 /// integer and returns the rounded values in a 128-bit vector of
54 /// A 128-bit vector of [4 x float] values to be rounded up.
55 /// \returns A 128-bit vector of [4 x float] containing the rounded values.
58 /// Rounds up each element of the 128-bit vector of [2 x double] to an
59 /// integer and returns the rounded values in a 128-bit vector of
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H A Davxvnniintrin.h1 /*===--------------- avxvnniintrin.h - VNNI intrinsics --------------------===
22 *===-----------------------------------------------------------------------===
46 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a __A with
47 /// corresponding signed 8-bit integers in \a __B, producing 4 intermediate signed
48 /// 16-bit results. Sum these 4 results with the corresponding 32-bit integer
49 /// in \a __S, and store the packed 32-bit results in DST.
57 /// tmp3.word := Signed(ZeroExtend16(__A.byte[4*j+2]) * SignExtend16(__B.byte[4*j+2]))
69 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a __A with
70 /// corresponding signed 8-bit integers in \a __B, producing 4 intermediate signed
71 /// 16-bit results. Sum these 4 results with the corresponding 32-bit integer
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H A Davxvnniint8intrin.h1 /*===-------- avxvnniint8intrin.h - AVXVNNIINT8 intrinsics -----------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
25 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in \a __A with
26 /// corresponding signed 8-bit integers in \a __B, producing 4 intermediate
27 /// signed 16-bit results. Sum these 4 results with the corresponding
28 /// 32-bit integer in \a __W, and store the packed 32-bit results in \a dst.
39 /// A 128-bit vector of [16 x char].
41 /// A 128-bit vector of [16 x char].
43 /// A 128-bit vector of [4 x int].
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/freebsd/contrib/wpa/src/common/
H A Dieee802_11_defs.h3 * Copyright (c) 2002-2019, Jouni Malinen <j@w1.fi>
4 * Copyright (c) 2007-2008 Intel Corporation
34 #define WLAN_FC_GET_TYPE(fc) (((fc) & 0x000c) >> 2)
39 #define WLAN_GET_SEQ_FRAG(seq) ((seq) & (BIT(3) | BIT(2) | BIT(1) | BIT(0)))
41 (((seq) & (~(BIT(3) | BIT(2) | BIT(1) | BIT(0)))) >> 4)
45 #define WLAN_FC_TYPE_DATA 2
51 #define WLAN_FC_STYPE_REASSOC_REQ 2
74 #define WLAN_FC_STYPE_DATA_CFPOLL 2
95 #define WLAN_AUTH_FT 2
105 #define WLAN_CAPABILITY_ESS BIT(0)
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H A Ddefs.h2 * WPA Supplicant - Common definitions
3 * Copyright (c) 2004-2018, Jouni Malinen <j@w1.fi>
12 #define WPA_CIPHER_NONE BIT(0)
13 #define WPA_CIPHER_WEP40 BIT(1)
14 #define WPA_CIPHER_WEP104 BIT(2)
15 #define WPA_CIPHER_TKIP BIT(3)
16 #define WPA_CIPHER_CCMP BIT(4)
17 #define WPA_CIPHER_AES_128_CMAC BIT(5)
18 #define WPA_CIPHER_GCMP BIT(6)
19 #define WPA_CIPHER_SMS4 BIT(7)
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/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drs.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022, 2024 Intel Corporation
12 * enum iwl_tlc_mng_cfg_flags - options for TLC config flags
22 * for BPSK (MCS 0) with 2 spatial
27 IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(
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/freebsd/sys/dev/msk/
H A Dif_mskreg.h17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
59 * 2. Redistributions in binary form must reproduce the above copyright
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
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/freebsd/sys/contrib/dev/rtw89/
H A Dpci.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
12 #define MDIO_PG0_G2 2
18 #define BAC_OOBS_SEL BIT(4)
20 #define B_BAC_EQ_SEL BIT(5)
22 #define B_PCIE_BIT_PSAVE BIT(15)
24 #define BAC_RX_TEST_EN BIT(
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/freebsd/sys/dev/flash/flexspi/
H A Dflex_spi.h1 /*-
10 * 2. Redistributions in binary form must reproduce the above copyright
29 #define BIT(x) (1 << (x)) macro
35 #define FSPI_MCR0_LEARN_EN BIT(15)
36 #define FSPI_MCR0_SCRFRUN_EN BIT(14)
37 #define FSPI_MCR0_OCTCOMB_EN BIT(13)
38 #define FSPI_MCR0_DOZE_EN BIT(12)
39 #define FSPI_MCR0_HSEN BIT(11)
40 #define FSPI_MCR0_SERCLKDIV BIT(8)
41 #define FSPI_MCR0_ATDF_EN BIT(7)
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
35 #define MT_HW_INFO_BASE ((dev)->reg_map[MT_HW_BASE])
40 #define MT_TOP_3NSS BIT(24)
45 #define MT_TOP_MISC2 ((dev)->reg_map[MT_TOP_CFG_BASE] + 0x134)
46 #define MT_TOP_MISC2_FW_STATE GENMASK(2, 0)
49 #define MT_TOP_MISC2_FW_PWR_ON BIT(1)
59 #define MT_MCU_PCIE_REMAP_2 ((dev)->reg_map[MT_PCIE_REMAP_2])
62 #define MT_PCIE_REMAP_BASE_2 ((dev)->reg_map[MT_PCIE_REMAP_BASE2])
67 #define MT_MCU_CIRQ_IRQ_SEL(n) MT_MCU_CIRQ((n) << 2)
69 #define MT_HIF(ofs) ((dev)->reg_map[MT_HIF_BASE] + (ofs))
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/freebsd/sys/contrib/dev/athk/ath10k/
H A Drx_desc.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
13 RX_ATTENTION_FLAGS_FIRST_MPDU = BIT(0),
14 RX_ATTENTION_FLAGS_LAST_MPDU = BIT(1),
15 RX_ATTENTION_FLAGS_MCAST_BCAST = BIT(2),
16 RX_ATTENTION_FLAGS_PEER_IDX_INVALID = BIT(3),
17 RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT = BIT(4),
18 RX_ATTENTION_FLAGS_POWER_MGMT = BIT(5),
19 RX_ATTENTION_FLAGS_NON_QOS = BIT(6),
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/freebsd/sys/dev/ice/
H A Dice_adminq_cmd.h1 /* SPDX-License-Identifier: BSD-3-Clause */
11 * 2. Redistributions in binary form must reproduce the above copyright
87 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
105 #define ICE_AQC_RES_ID_SDP 2
110 #define ICE_AQC_RES_ACCESS_WRITE 2
127 #define ICE_AQ_RES_GLBL_DONE 2
128 u8 reserved[2];
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/freebsd/sys/dev/qat/qat_hw/qat_c62x/
H A Dadf_c62x_hw_data.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
9 #define ADF_C62X_ETR_BAR 2
23 #define ADF_C62X_POWERGATE_PKE BIT(24)
24 #define ADF_C62X_POWERGATE_DC BIT(23)
29 #define ADF_C62X_ENABLE_AE_ECC_ERR BIT(28)
30 #define ADF_C62X_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
35 #define ADF_C62X_ERRSSMSH_EN (BIT(3))
36 /* BIT(2) enables the logging of push/pull data errors. */
37 #define ADF_C62X_PPERR_EN (BIT(2))
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/freebsd/sys/powerpc/fpu/
H A Dfpu_sqrt.c3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
23 * 2. Redistributions in binary form must reproduce the above copyright
60 * x = mant * 2 (where 1 <= mant < 2 and exp is an integer)
65 * exp-1
66 * x = (2 * mant) * 2 (where 2 <= 2 * mant < 4)
71 * exp/2
72 * sqrt(x) = sqrt(mant) * 2
77 * (exp-1)/2
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/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_inline.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
19 #define ADF_C4XXX_SADB_SIZE_BIT BIT(24)
21 ((accel_dev)->aram_info->sadb_region_size / 32)
24 /* SADB CTRL register bit offsets */
39 #define ADF_C4XXX_STATS_REQUEST_ENABLED BIT(16)
40 #define ADF_C4XXX_STATS_REQUEST_DISABLED ~BIT(16)
45 #define ADF_C4XXX_MAC_STATS_READY BIT(0)
48 #define ADF_C4XXX_MAC_ERROR_TX_UNDERRUN BIT(6)
49 #define ADF_C4XXX_MAC_ERROR_TX_FCS BIT(7)
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H A Dadf_c4xxx_hw_data.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
11 #define ADF_C4XXX_ETR_BAR 2
32 #define ADF_C4XXX_FUSE_PROD_SKU_MASK BIT(31)
34 #define ADF_C4XXX_LEGFUSE_BASE_SKU_MASK (BIT(2) | BIT(3))
36 #define ADF_C4XXX_FUSE_DISABLE_INLINE_INGRESS BIT(12)
37 #define ADF_C4XXX_FUSE_DISABLE_INLINE_EGRESS BIT(13)
61 #define ADF_C4XXX_ENABLE_AE_ECC_ERR BIT(28)
62 #define ADF_C4XXX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
64 #define ADF_C4XXX_UERRSSMSH_INTS_CLEAR_MASK (~BIT(0) ^ BIT(16))
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/freebsd/sys/dev/qat/qat_hw/qat_200xx/
H A Dadf_200xx_hw_data.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
22 #define ADF_200XX_POWERGATE_PKE BIT(24)
23 #define ADF_200XX_POWERGATE_CY BIT(23)
30 #define ADF_200XX_ENABLE_AE_ECC_ERR BIT(28)
31 #define ADF_200XX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
34 #define ADF_200XX_ERRSSMSH_EN BIT(3)
38 /* BIT(2) enables the logging of push/pull data errors. */
39 #define ADF_200XX_PPERR_EN (BIT(2))
47 #define ADF_200XX_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0))
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/freebsd/sys/dev/qat/qat_hw/qat_c3xxx/
H A Dadf_c3xxx_hw_data.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
22 #define ADF_C3XXX_POWERGATE_PKE BIT(24)
23 #define ADF_C3XXX_POWERGATE_CY BIT(23)
28 #define ADF_C3XXX_ENABLE_AE_ECC_ERR BIT(28)
29 #define ADF_C3XXX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
32 #define ADF_C3XXX_ERRSSMSH_EN BIT(3)
36 /* BIT(2) enables the logging of push/pull data errors. */
37 #define ADF_C3XXX_PPERR_EN (BIT(2))
45 #define ADF_C3XXX_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0))
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/freebsd/sys/amd64/vmm/amd/
H A Damdvi_priv.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
16 * 2. Redistributions in binary form must reproduce the above copyright
37 #define BIT(n) (1ULL << (n)) macro
38 /* Return value of bits[n:m] where n and (n >= ) m are bit positions. */
40 ((1 << (((n) - (m)) + 1)) - 1))
45 #define AMDVI_PCI_CAP_IOTLB BIT(0) /* IOTLB is supported. */
46 #define AMDVI_PCI_CAP_HT BIT(1) /* HyperTransport tunnel support. */
47 #define AMDVI_PCI_CAP_NPCACHE BIT(2) /* Not present page cached. */
48 #define AMDVI_PCI_CAP_EFR BIT(3) /* Extended features. */
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