Lines Matching +full:2 +full:- +full:bit
17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
59 * 2. Redistributions in binary form must reproduce the above copyright
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
189 #define BIT_2 (1 << 2)
222 #define SHIFT2(x) ((x) << 2)
229 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
230 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
231 #define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
232 #define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
233 #define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */
234 #define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */
235 #define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */
236 #define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */
237 #define PCI_CFG_REG_0 0x90 /* 32 bit Config Register 0 */
238 #define PCI_CFG_REG_1 0x94 /* 32 bit Config Register 1 */
241 #define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */
242 #define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */
243 #define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */
244 #define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */
245 #define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */
246 #define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */
247 #define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */
248 #define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */
249 #define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */
252 #define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */
253 #define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */
254 #define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */
255 #define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */
256 #define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */
257 #define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */
258 #define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */
259 #define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */
261 /* PCI_OUR_REG_1 32 bit Our Register 1 */
262 #define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */
263 #define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */
264 #define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */
265 #define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */
266 #define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */
267 #define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */
273 #define PCI_PAGESIZE (3L<<20)/* Bit 21..20: FLASH Page Size */
276 #define PCI_PAGE_64K (2L<<20)/* 64 k pages */
278 #define PCI_PAGEREG (7L<<16)/* Bit 18..16: Page Register */
279 #define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */
287 #define PCI_SKEW_DAS (0xfL<<4)/* Bit 7.. 4: Skew Ctrl, DAS Ext */
288 #define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */
289 #define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */
291 /* PCI_OUR_REG_2 32 bit Our Register 2 */
292 #define PCI_VPD_WR_THR (0xff<<24) /* Bit 31..24: VPD Write Threshold */
293 #define PCI_DEV_SEL (0x7f<<17) /* Bit 23..17: EEPROM Device Select */
294 #define PCI_VPD_ROM_SZ (0x07<<14) /* Bit 16..14: VPD ROM Size */
295 /* Bit 13..12: reserved */
296 #define PCI_PATCH_DIR (0x0f<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */
301 #define PCI_EXT_PATCHS (0x0f<<4) /* Bit 7.. 4: Extended Patches 3..0 */
308 #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */
310 /* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */
312 #define PCI_OS_PCIX BIT_30 /* PCI-X Bus */
313 #define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */
315 #define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */
316 #define PCI_OS_DLLE_MSK (3<<24) /* Bit 25..24: DLL Status Indication */
317 #define PCI_OS_DLLR_MSK (0x0f<<20) /* Bit 23..20: DLL Row Counters Values */
318 #define PCI_OS_DLLC_MSK (0x0f<<16) /* Bit 19..16: DLL Col. Counters Values */
320 #define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */
323 #define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */
324 #define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */
325 #define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */
327 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
330 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
331 #define PCI_TIMER_VALUE_MSK (0xff<<16) /* Bit 23..16: Timer Value Mask */
342 /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
343 /* Bit 31..27: for A3 & later */
345 #define PCI_CTL_SRESET_VMAIN_AV BIT_30 /* Soft Reset for Vmain_av De-Glitch */
346 #define PCI_CTL_BYPASS_VMAIN_AV BIT_29 /* Bypass En. for Vmain_av De-Glitch */
347 #define PCI_CTL_TIM_VMAIN_AV1 BIT_28 /* Bit 28..27: Timer Vmain_av Mask */
348 #define PCI_CTL_TIM_VMAIN_AV0 BIT_27 /* Bit 28..27: Timer Vmain_av Mask */
350 /* Bit 26..16: Release Clock on Event */
351 #define PCI_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */
362 /* Bit 10.. 0: Mask for Gate Clock */
369 #define PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */
375 /* PCI_CFG_REG_1 32 bit Config Register 1 */
377 /* Bit 23..21: Release Clock on Event */
380 #define PCI_CF1_REL_PCIE_RESET BIT_21 /* PCI-E reset */
381 /* Bit 20..18: Gate Clock on Event */
383 #define PCI_CF1_GAT_PCIE_RX_IDLE BIT_19 /* PCI-E Rx Electrical idle */
384 #define PCI_CF1_GAT_PCIE_RESET BIT_18 /* PCI-E Reset */
385 #define PCI_CF1_PRST_PHY_CLKREQ BIT_17 /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
386 #define PCI_CF1_PCIE_RST_CLKREQ BIT_16 /* Enable PCI-E rst generate CLKREQ */
392 /* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */
393 #define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */
398 #define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */
402 #define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */
407 /* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */
411 #define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */
412 #define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */
414 /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
431 #define B0_RAP 0x0000 /* 8 bit Register Address Port */
432 #define B0_CTST 0x0004 /* 16 bit Control/Status register */
433 #define B0_LED 0x0006 /* 8 Bit LED register */
434 #define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */
435 #define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */
436 #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */
437 #define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */
438 #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */
439 #define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */
441 /* Special ISR registers (Yukon-2 only) */
442 #define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */
443 #define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */
444 #define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Reg */
445 #define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Reg */
446 #define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */
450 * - completely empty (this is the RAP Block window)
455 * Bank 2
457 /* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */
459 #define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */
461 #define B2_CONN_TYP 0x0118 /* 8 bit Connector type */
462 #define B2_PMD_TYP 0x0119 /* 8 bit PMD type */
463 #define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */
464 #define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */
465 #define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */
466 #define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */
467 #define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */
468 #define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */
469 #define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */
470 #define B2_TI_INI 0x0130 /* 32 bit Timer Init Value */
471 #define B2_TI_VAL 0x0134 /* 32 bit Timer Value */
472 #define B2_TI_CTRL 0x0138 /* 8 bit Timer Control */
473 #define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */
474 #define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/
475 #define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */
476 #define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */
477 #define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */
478 #define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */
479 #define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */
480 #define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */
481 #define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */
482 #define B2_GP_IO 0x015c /* 32 bit General Purpose I/O Register */
483 #define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */
484 #define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */
485 #define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */
486 #define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */
488 #define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */
489 #define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */
495 #define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */
496 #define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */
497 #define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */
499 #define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */
502 /* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */
504 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
508 #define B3_RI_WTO_R1 0x0190 /* 8 bit WR Timeout Queue R1 (TO0) */
509 #define B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */
510 #define B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */
511 #define B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */
512 #define B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */
513 #define B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */
514 #define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */
515 #define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */
516 #define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */
517 #define B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */
518 #define B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10)*/
519 #define B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11)*/
520 #define B3_RI_TO_VAL 0x019c /* 8 bit Current Timeout Count Val */
521 #define B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */
522 #define B3_RI_TEST 0x01a2 /* 8 bit RAM Interface Test Register */
525 * Bank 4 - 5
527 /* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
528 #define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/
529 #define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */
530 #define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */
531 #define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */
532 #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */
533 #define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */
534 #define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */
538 /* RSS key registers for Yukon-2 Family */
539 #define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */
543 #define KEY_IDX_2 8 /* offset for location of KEY 2 */
545 /* 0x0280 - 0x0292: MAC 2 */
550 * Bank 8 - 15
556 #define Q_D 0x00 /* 8*32 bit Current Descriptor */
557 #define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */
558 #define Q_DONE 0x24 /* 16 bit Done Index */
559 #define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */
560 #define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */
561 #define Q_BC 0x30 /* 32 bit Current Byte Counter */
562 #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */
563 #define Q_F 0x38 /* 32 bit Flag Register */
564 #define Q_T1 0x3c /* 32 bit Test Register 1 */
565 #define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */
566 #define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */
567 #define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */
568 #define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */
569 #define Q_WM 0x40 /* 16 bit FIFO Watermark */
570 #define Q_AL 0x42 /* 8 bit FIFO Alignment */
571 #define Q_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */
572 #define Q_RSL 0x46 /* 8 bit FIFO Read Shadow Level */
573 #define Q_RP 0x48 /* 8 bit FIFO Read Pointer */
574 #define Q_RL 0x4a /* 8 bit FIFO Read Level */
575 #define Q_WP 0x4c /* 8 bit FIFO Write Pointer */
576 #define Q_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */
577 #define Q_WL 0x4e /* 8 bit FIFO Write Level */
578 #define Q_WSL 0x4f /* 8 bit FIFO Write Shadow Level */
585 #define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */
586 #define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */
587 #define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */
588 #define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/
589 #define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */
590 #define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */
591 #define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */
592 #define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */
593 #define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */
594 #define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */
601 * Bank 16 - 23
607 #define RB_START 0x00 /* 32 bit RAM Buffer Start Address */
608 #define RB_END 0x04 /* 32 bit RAM Buffer End Address */
609 #define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */
610 #define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */
611 #define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */
612 #define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */
613 #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */
614 #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */
615 #define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */
616 #define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */
617 #define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */
618 #define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */
619 #define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */
624 /* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
625 #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */
626 #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */
627 #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */
628 #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */
629 #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */
630 #define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */
631 #define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
632 #define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
633 #define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */
634 #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
635 #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
636 #define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
637 #define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
642 /* 0x0c80 - 0x0cbf: MAC 2 */
643 /* 0x0cc0 - 0x0cff: reserved */
648 /* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
649 #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */
650 #define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
651 #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */
652 #define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */
653 #define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */
654 #define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */
655 #define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */
656 #define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */
657 #define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */
658 #define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */
663 /* 0x0d80 - 0x0dbf: MAC 2 */
664 /* 0x0daa - 0x0dff: reserved */
670 #define B28_DPT_INI 0x0e00 /* 24 bit Descriptor Poll Timer Init Val */
671 #define B28_DPT_VAL 0x0e04 /* 24 bit Descriptor Poll Timer Curr Val */
672 #define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */
673 #define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg */
675 #define GMAC_TI_ST_VAL 0x0e14 /* 32 bit Time Stamp Timer Curr Val */
676 #define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */
677 #define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */
678 /* Polling Unit Registers (Yukon-2 only) */
679 #define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */
680 #define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */
681 #define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */
682 #define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */
683 /* ASF Subsystem Registers (Yukon-2 only) */
684 #define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */
685 #define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */
686 #define B28_Y2_CPU_WDOG 0x0e48 /* 32 bit Watchdog Register */
687 #define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */
688 #define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */
689 #define B28_Y2_ASF_HCU_CCSR 0x0e68 /* 32 bit ASF HCU CCSR (Yukon EX) */
690 #define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */
691 #define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */
692 #define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */
693 #define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */
694 #define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */
700 /* Status BMU Registers (Yukon-2 only)*/
701 #define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */
702 #define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */
703 #define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */
704 #define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */
705 #define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */
706 #define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */
707 #define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */
708 #define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */
709 #define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */
710 #define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */
711 /* FIFO Control/Status Registers (Yukon-2 only)*/
712 #define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */
713 #define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */
714 #define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */
715 #define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */
716 #define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */
717 #define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */
718 #define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */
719 /* Level and ISR Timer Registers (Yukon-2 only)*/
720 #define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */
721 #define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */
722 #define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */
723 #define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */
724 #define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */
725 #define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */
726 #define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */
727 #define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */
728 #define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */
729 #define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */
730 #define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */
731 #define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */
742 #define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */
743 #define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */
744 #define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */
745 #define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */
746 #define GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */
748 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
750 #define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */
752 #define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */
753 #define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */
754 #define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */
755 #define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */
756 #define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */
757 #define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */
758 #define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */
759 #define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */
763 #define WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */
764 #define WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */
768 #define WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */
769 #define WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */
772 * Bank 32 - 33
775 #define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */
777 /* offset to configuration space on Yukon-2 */
780 #define BASE_GMAC_2 0x3800 /* GMAC 2 registers */
783 * Control Register Bit Definitions:
785 /* B0_CTST 24 bit Control/Status register */
786 #define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */
787 #define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */
788 #define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */
789 #define Y2_HW_WOL_OFF BIT_14 /* HW WOL Off (Yukon-EC Ultra A1 only) */
790 #define Y2_ASF_ENABLE BIT_13 /* ASF Unit Enable (YUKON-2 only) */
791 #define Y2_ASF_DISABLE BIT_12 /* ASF Unit Disable (YUKON-2 only) */
792 #define Y2_CLK_RUN_ENA BIT_11 /* CLK_RUN Enable (YUKON-2 only) */
793 #define Y2_CLK_RUN_DIS BIT_10 /* CLK_RUN Disable (YUKON-2 only) */
794 #define Y2_LED_STAT_ON BIT_9 /* Status LED On (YUKON-2 only) */
795 #define Y2_LED_STAT_OFF BIT_8 /* Status LED Off (YUKON-2 only) */
799 #define CS_STOP_MAST BIT_4 /* Command Bit to stop the master */
808 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
818 /* B0_ISRC 32 bit Interrupt Source Register */
819 /* B0_IMSK 32 bit Interrupt Mask Register */
820 /* B0_SP_ISRC 32 bit Special Interrupt Source Reg */
821 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
822 /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
823 /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
824 /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
825 /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
834 #define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */
835 #define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */
836 #define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */
837 #define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */
838 #define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */
850 #define Y2_IS_L2_MASK 0x00001f00 /* IRQ Mask for port 2 */
859 /* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */
860 /* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */
861 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
866 #define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */
867 #define Y2_IS_PCI_NEXP BIT_24 /* PCI-Express error similar to PCI error */
871 #define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */
890 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
891 #define CFG_CHIP_R_MSK (0x0f<<4) /* Bit 7.. 4: Chip Revision */
892 #define CFG_DIS_M2_CLK BIT_1 /* Disable Clock for 2nd MAC */
893 #define CFG_SNG_MAC BIT_0 /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */
895 /* B2_CHIP_ID 8 bit Chip Identification Number */
898 #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */
899 #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */
900 #define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */
901 #define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */
902 #define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */
903 #define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */
904 #define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */
905 #define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */
906 #define CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */
907 #define CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */
909 #define CHIP_ID_YUKON_OPT 0xbc /* Chip ID for YUKON-2 Optima */
911 #define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */
912 #define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */
913 #define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */
914 #define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */
916 #define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */
917 #define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */
918 #define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */
921 #define CHIP_REV_YU_EC_U_A1 2
923 #define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */
925 #define CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-2 EX A0 */
926 #define CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-2 EX B0 */
928 #define CHIP_REV_YU_SU_A0 0 /* Chip Rev. for Yukon-2 SUPR A0 */
929 #define CHIP_REV_YU_SU_B0 1 /* Chip Rev. for Yukon-2 SUPR B0 */
930 #define CHIP_REV_YU_SU_B1 3 /* Chip Rev. for Yukon-2 SUPR B1 */
932 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
933 #define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */
934 #define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */
935 #define Y2_COR_CLK_LNK2_DIS BIT_5 /* Disable Core clock Link 2 */
936 #define Y2_PCI_CLK_LNK2_DIS BIT_4 /* Disable PCI clock Link 2 */
942 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
943 #define CFG_LED_MODE_MSK (0x07<<2) /* Bit 4.. 2: LED Mode Mask */
944 #define CFG_LINK_2_AVAIL BIT_1 /* Link 2 available */
947 #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
950 /* B2_E_3 8 bit lower 4 bits used for HW self test result */
953 /* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */
954 /* Yukon-EC/FE */
955 #define Y2_CLK_DIV_VAL_MSK (0xff<<16) /* Bit 23..16: Clock Divisor Value */
957 /* Yukon-2 */
958 #define Y2_CLK_DIV_VAL2_MSK (0x07<<21) /* Bit 23..21: Clock Divisor Value */
959 #define Y2_CLK_SELECT2_MSK (0x1f<<16) /* Bit 20..16: Clock Select */
965 /* B2_TI_CTRL 8 bit Timer control */
966 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
971 /* B2_TI_TEST 8 Bit Timer Test */
972 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
973 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
978 /* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */
979 /* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */
980 #define DPT_MSK 0x00ffffff /* Bit 23.. 0: Desc Poll Timer Bits */
982 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
986 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
1006 #define GLB_GPIO_RAND_BIT_1 BIT_9 /* Random Bit 1 */
1008 /* B2_I2C_CTRL 32 bit I2C HW Control Register */
1010 #define I2C_ADDR (0x7fff<<16) /* Bit 30..16: Addr to be RD/WR */
1011 #define I2C_DEV_SEL (0x7f<<9) /* Bit 15.. 9: I2C Device Select */
1013 #define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */
1016 #define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */
1024 /* B2_I2C_IRQ 32 bit I2C HW IRQ Register */
1027 /* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */
1036 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
1040 /* B2_BSC_STAT 8 bit Blink Source Counter Status */
1043 /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
1048 /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
1052 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
1053 #define RAM_ADR_RAN 0x0007ffff /* Bit 18.. 0: RAM Address Range */
1056 /* B3_RI_CTRL 16 bit RAM Interface Control Register */
1064 /* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
1065 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
1066 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
1067 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
1068 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
1069 #define TXA_MAX_VAL 0x00ffffff/* Bit 23.. 0: Max TXA Timer/Cnt Val */
1071 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
1081 /* TXA_TEST 8 bit Tx Arbiter Test Register */
1089 /* TXA_STAT 8 bit Tx Arbiter Status Register */
1092 /* Q_BC 32 bit Current Byte Counter */
1093 #define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */
1095 /* Rx BMU Control / Status Registers (Yukon-2) */
1121 /* Tx BMU Control / Status Registers (Yukon-2) */
1122 /* Bit 31: same as for Rx */
1126 /* Bit 10..0: same as for Rx */
1128 /* Q_F 32 bit Flag Register */
1129 #define F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/
1130 #define F_TX_CHK_AUTO_ON BIT_30 /* Tx checksum auto-calc On(Yukon EX)*/
1133 #define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */
1137 /* Bit 23..16: # of Qwords in FIFO */
1138 #define F_WATER_MARK 0x0007ff/* Bit 10.. 0: Watermark */
1140 /* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
1141 /* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */
1148 /* RB_START 32 bit RAM Buffer Start Address */
1149 /* RB_END 32 bit RAM Buffer End Address */
1150 /* RB_WP 32 bit RAM Buffer Write Pointer */
1151 /* RB_RP 32 bit RAM Buffer Read Pointer */
1152 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
1153 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
1154 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
1155 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
1156 /* RB_PC 32 bit RAM Buffer Packet Counter */
1157 /* RB_LEV 32 bit RAM Buffer Level Register */
1158 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
1160 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
1166 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
1174 /* RB_CTRL 8 bit RAM Buffer Control Register */
1187 /* Threshold values for Yukon-EC Ultra */
1201 #define Q_R2 0x0080 /* Receive Queue 2 */
1204 #define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */
1205 #define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */
1208 #define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */
1210 #define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */
1221 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1247 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
1250 /* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */
1256 * Marvel-PHY Registers, indirect addressed over GMAC
1258 #define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */
1259 #define PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */
1260 #define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
1261 #define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
1262 #define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
1263 #define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
1264 #define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
1265 #define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */
1266 #define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
1267 /* Marvel-specific registers */
1268 #define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
1269 #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
1270 /* 0x0b - 0x0e: reserved */
1271 #define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
1272 #define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */
1273 #define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */
1274 #define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */
1275 #define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */
1276 #define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */
1277 #define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */
1278 #define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */
1279 #define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */
1280 #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */
1281 #define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */
1282 #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1283 #define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */
1284 #define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */
1285 #define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */
1286 #define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */
1289 #define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */
1290 #define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */
1291 #define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */
1292 #define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */
1293 #define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */
1295 #define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */
1296 #define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */
1297 #define PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */
1298 #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */
1299 #define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */
1300 #define PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */
1301 #define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */
1302 #define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */
1303 #define PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */
1304 #define PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */
1310 #define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */
1311 #define PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */
1312 #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */
1313 #define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occurred */
1314 #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */
1315 #define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */
1316 #define PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */
1317 #define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */
1319 #define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */
1320 #define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */
1321 #define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */
1327 #define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */
1328 #define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */
1329 #define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */
1330 #define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */
1331 #define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */
1333 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1334 #define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */
1335 #define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */
1336 #define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */
1337 #define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */
1338 #define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */
1339 #define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */
1340 #define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */
1342 /***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1343 /***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/
1349 #define PHY_M_AN_100_T4 BIT_9 /* Not cap. 100Base-T4 (always 0) */
1350 #define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */
1351 #define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */
1352 #define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */
1353 #define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */
1354 #define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */
1359 #define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */
1360 #define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */
1363 #define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */
1364 #define PHY_M_P_SYM_MD_X (1<<7) /* Bit 8.. 7: symmetric Pause Mode */
1365 #define PHY_M_P_ASYM_MD_X (2<<7) /* Bit 8.. 7: asymmetric Pause Mode */
1366 #define PHY_M_P_BOTH_MD_X (3<<7) /* Bit 8.. 7: both Pause Mode */
1368 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1369 #define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
1372 #define PHY_M_1000C_MPD BIT_10 /* Multi-Port Device */
1376 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1377 #define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */
1378 #define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
1381 #define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */
1383 #define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */
1390 #define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */
1391 #define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */
1399 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1401 #define PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */
1406 /* 000=1x; 001=2x; 010=3x; 011=4x */
1418 #define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */
1420 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1421 #define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */
1429 #define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */
1444 /***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1445 /***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1446 #define PHY_M_IS_AN_ERROR BIT_15 /* Auto-Negotiation Error */
1450 #define PHY_M_IS_AN_COMPL BIT_11 /* Auto-Negotiation Completed */
1465 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1469 #define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */
1471 #define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */
1473 #define PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */
1478 #define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */
1479 #define PHY_M_EC_FIB_AN_ENA BIT_3 /* Fiber Auto-Neg. Enable (88E1011S only) */
1485 /* 00=1x; 01=2x; 10=3x; 11=4x */
1487 /* 00=dis; 01=1x; 10=2x; 11=3x */
1492 /* 000=1x; 001=2x; 010=3x; 011=4x */
1494 #define MAC_TX_CLK_0_MHZ 2
1498 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1500 #define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */
1502 #define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */
1505 #define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */
1507 #define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */
1519 #define PULS_42MS 2 /* 42 ms to 84 ms */
1530 #define BLINK_170MS 2 /* 170 ms */
1534 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1535 #define PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */
1536 #define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */
1537 #define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */
1538 #define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */
1539 #define PHY_M_LED_MO_1000(x) SHIFT4(x) /* Bit 5.. 4: Link 1000 */
1540 #define PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */
1541 #define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */
1545 #define MO_LED_OFF 2
1548 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1553 #define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */
1555 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1564 #define PHY_M_UNDOC1 BIT_7 /* undocumented bit !! */
1566 #define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1568 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
1572 #define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */
1573 #define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */
1575 #define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */
1580 #define CABD_STAT_OPEN 2
1584 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1585 #define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */
1586 #define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */
1587 #define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */
1610 /***** PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1613 #define PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */
1615 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1616 /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
1621 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1622 #define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */
1623 #define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */
1625 #define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */
1628 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1629 #define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */
1630 #define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */
1631 #define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1632 #define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1639 /***** PHY_MARV_PHY_STAT (page 3) 16 bit r/w Polarity Control Reg. *****/
1640 #define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */
1641 #define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1642 #define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1643 #define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1644 #define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1645 #define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1659 * therefore ALL registers will be addressed with 16 bit accesses.
1665 #define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */
1666 #define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */
1667 #define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */
1668 #define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */
1669 #define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */
1670 #define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */
1671 #define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */
1674 #define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */
1675 #define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */
1676 #define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */
1677 #define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */
1678 #define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */
1679 #define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */
1682 #define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */
1683 #define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */
1684 #define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */
1685 #define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */
1688 #define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */
1689 #define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */
1690 #define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */
1693 #define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */
1694 #define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */
1695 #define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1698 #define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */
1699 #define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */
1700 #define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */
1707 * MIB Counters base address definitions (low word) -
1708 * use offset 4 for access to high word (32 bit r/o)
1737 (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */
1739 (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */
1741 (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */
1743 (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */
1745 (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */
1747 (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */
1753 (GM_MIB_CNT_BASE + 168) /* Rx spare 2 */
1773 (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */
1775 (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */
1777 (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */
1779 (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */
1781 (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */
1783 (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */
1799 /*----------------------------------------------------------------------------*/
1801 * GMAC Bit Definitions
1803 * If the bit access behaviour differs from the register access behaviour
1804 * (r/w, r/o) this is documented after the bit number.
1805 * The following bit access behaviours are used:
1810 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1813 #define GM_GPSR_FC_TX_DIS BIT_13 /* Tx Flow-Control Mode Disabled */
1822 #define GM_GPSR_FC_RX_DIS BIT_2 /* Rx Flow-Control Mode Disabled */
1824 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1825 #define GM_GPCR_RMII_PH_ENA BIT_15 /* Enable RMII for PHY (Yukon-FE only) */
1826 #define GM_GPCR_RMII_LB_ENA BIT_14 /* Enable RMII Loopback (Yukon-FE only) */
1827 #define GM_GPCR_FC_TX_DIS BIT_13 /* Disable Tx Flow-Control Mode */
1835 #define GM_GPCR_FC_RX_DIS BIT_4 /* Disable Rx Flow-Control Mode */
1837 #define GM_GPCR_AU_DUP_DIS BIT_2 /* Disable Auto-Update Duplex */
1838 #define GM_GPCR_AU_FCT_DIS BIT_1 /* Disable Auto-Update Flow-C. */
1839 #define GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */
1845 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1846 #define GM_TXCR_FORCE_JAM BIT_15 /* Force Jam / Flow-Control */
1849 #define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */
1850 #define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */
1851 /* (Yukon-2 only) */
1856 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1859 #define GM_RXCR_CRC_DIS BIT_13 /* Remove 4-byte CRC */
1860 #define GM_RXCR_PASS_FC BIT_12 /* Pass FC packets to FIFO (Yukon-1 only) */
1862 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1863 #define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */
1864 #define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */
1865 #define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */
1866 #define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */
1867 /* (Yukon-2 only) */
1879 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1880 #define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */
1881 /* r/o on Yukon, r/w on Yukon-EC */
1885 #define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */
1893 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1894 #define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */
1895 #define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */
1903 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1908 #define GMR_FS_LEN_MSK (0xffff<<16) /* Bit 31..16: Rx Frame Length */
1915 #define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */
1916 #define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */
1941 /* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */
1942 /* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */
1943 /* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */
1944 /* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */
1945 /* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */
1946 /* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */
1947 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
1948 /* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
1949 /* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */
1950 /* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */
1951 /* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */
1952 /* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */
1953 /* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */
1954 /* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */
1956 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1982 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
1983 #define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */
1984 #define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */
1987 #define TX_JUMBO_ENA BIT_23 /* Enable Jumbo Mode (Yukon-EC Ultra) */
1988 #define TX_JUMBO_DIS BIT_22 /* Disable Jumbo Mode (Yukon-EC Ultra) */
2004 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
2009 /* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */
2017 /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
2025 #define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */
2028 /* B28_Y2_ASF_HCU_CCSR 32bit CPU Control and Status Register (Yukon EX) */
2050 /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
2055 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
2062 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
2080 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
2081 #define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */
2087 #define GPC_HWCFG_M_2 BIT_22 /* HWCFG_MODE[2] */
2094 #define GPC_ANEG_2 BIT_15 /* ANEG[2] */
2097 #define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */
2098 #define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */
2099 #define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */
2100 #define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */
2101 #define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */
2105 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
2106 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
2116 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
2125 bus_write_4((sc)->msk_res[0], (reg), (val))
2127 bus_write_2((sc)->msk_res[0], (reg), (val))
2129 bus_write_1((sc)->msk_res[0], (reg), (val))
2132 bus_read_4((sc)->msk_res[0], (reg))
2134 bus_read_2((sc)->msk_res[0], (reg))
2136 bus_read_1((sc)->msk_res[0], (reg))
2139 bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2141 bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2143 bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2146 bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2148 bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2150 bus_read_1((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2153 CSR_READ_4((sc_if)->msk_softc, (reg))
2155 CSR_READ_2((sc_if)->msk_softc, (reg))
2157 CSR_READ_1((sc_if)->msk_softc, (reg))
2160 CSR_WRITE_4((sc_if)->msk_softc, (reg), (val))
2162 CSR_WRITE_2((sc_if)->msk_softc, (reg), (val))
2164 CSR_WRITE_1((sc_if)->msk_softc, (reg), (val))
2167 ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg))
2208 /* mask and shift value to get Tx async queue status for port 2 */
2215 /* mask and shift value to get Tx sync queue status for port 2 */
2221 /* YUKON-2 bit values */
2227 /* YUKON-2 Control flags */
2244 /* YUKON-2 Rx/Tx opcodes defines */
2265 /* YUKON-2 STATUS opcodes defines */
2275 /* YUKON-2 SPECIAL opcodes defines */
2292 /* Descriptor Bit Definition */
2295 #define BMU_OWN BIT_31 /* OWN bit: 0=host/1=BMU */
2303 #define BMU_SW BIT_24 /* (Tx) 1 bit res. for SW use */
2308 /* Bit 23..16: BMU Check Opcodes */
2312 #define BMU_BBC 0xffff /* Bit 15.. 0: Buffer Byte Counter */
2315 * Controller requires an additional LE op code for 64bit DMA operation.
2317 * reduces number of available RX buffers with 64bit DMA so double
2318 * number of RX buffers on platforms that support 64bit DMA. For TX
2323 * allocates 50% more total TX buffers on platforms that support 64bit
2357 #define MSK_JUMBO_MTU (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2359 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)
2360 #define MSK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
2412 ((sc)->msk_rdata.msk_tx_ring_paddr + sizeof(struct msk_tx_desc) * (i))
2414 ((sc)->msk_rdata.msk_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i))
2416 ((sc)->msk_rdata.msk_jumbo_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i))
2427 #define MSK_RX_INC(x, y) (x) = (x + 2) % y
2428 #define MSK_RX_BUF_CNT (MSK_RX_RING_CNT / 2)
2429 #define MSK_JUMBO_RX_BUF_CNT (MSK_JUMBO_RX_RING_CNT / 2)
2438 #define MSK_PEX_BUS 2
2440 #define MSK_PROC_DEFAULT (MSK_RX_RING_CNT / 2)
2442 #define MSK_PROC_MAX (MSK_RX_RING_CNT - 1)
2524 struct msk_if_softc *msk_if[2];
2525 device_t msk_devs[2];
2528 int msk_txqstart[2];
2529 int msk_txqend[2];
2530 int msk_rxqstart[2];
2531 int msk_rxqend[2];
2543 #define MSK_LOCK(_sc) mtx_lock(&(_sc)->msk_mtx)
2544 #define MSK_UNLOCK(_sc) mtx_unlock(&(_sc)->msk_mtx)
2545 #define MSK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->msk_mtx, MA_OWNED)
2546 #define MSK_IF_LOCK(_sc) MSK_LOCK((_sc)->msk_softc)
2547 #define MSK_IF_UNLOCK(_sc) MSK_UNLOCK((_sc)->msk_softc)
2548 #define MSK_IF_LOCK_ASSERT(_sc) MSK_LOCK_ASSERT((_sc)->msk_softc)
2550 #define MSK_USECS(sc, us) ((sc)->msk_clock * (us))