Lines Matching +full:2 +full:- +full:bit
1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
13 RX_ATTENTION_FLAGS_FIRST_MPDU = BIT(0),
14 RX_ATTENTION_FLAGS_LAST_MPDU = BIT(1),
15 RX_ATTENTION_FLAGS_MCAST_BCAST = BIT(2),
16 RX_ATTENTION_FLAGS_PEER_IDX_INVALID = BIT(3),
17 RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT = BIT(4),
18 RX_ATTENTION_FLAGS_POWER_MGMT = BIT(5),
19 RX_ATTENTION_FLAGS_NON_QOS = BIT(6),
20 RX_ATTENTION_FLAGS_NULL_DATA = BIT(7),
21 RX_ATTENTION_FLAGS_MGMT_TYPE = BIT(8),
22 RX_ATTENTION_FLAGS_CTRL_TYPE = BIT(9),
23 RX_ATTENTION_FLAGS_MORE_DATA = BIT(10),
24 RX_ATTENTION_FLAGS_EOSP = BIT(11),
25 RX_ATTENTION_FLAGS_U_APSD_TRIGGER = BIT(12),
26 RX_ATTENTION_FLAGS_FRAGMENT = BIT(13),
27 RX_ATTENTION_FLAGS_ORDER = BIT(14),
28 RX_ATTENTION_FLAGS_CLASSIFICATION = BIT(15),
29 RX_ATTENTION_FLAGS_OVERFLOW_ERR = BIT(16),
30 RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR = BIT(17),
31 RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL = BIT(18),
32 RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL = BIT(19),
33 RX_ATTENTION_FLAGS_SA_IDX_INVALID = BIT(20),
34 RX_ATTENTION_FLAGS_DA_IDX_INVALID = BIT(21),
35 RX_ATTENTION_FLAGS_SA_IDX_TIMEOUT = BIT(22),
36 RX_ATTENTION_FLAGS_DA_IDX_TIMEOUT = BIT(23),
37 RX_ATTENTION_FLAGS_ENCRYPT_REQUIRED = BIT(24),
38 RX_ATTENTION_FLAGS_DIRECTED = BIT(25),
39 RX_ATTENTION_FLAGS_BUFFER_FRAGMENT = BIT(26),
40 RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR = BIT(27),
41 RX_ATTENTION_FLAGS_TKIP_MIC_ERR = BIT(28),
42 RX_ATTENTION_FLAGS_DECRYPT_ERR = BIT(29),
43 RX_ATTENTION_FLAGS_FCS_ERR = BIT(30),
44 RX_ATTENTION_FLAGS_MSDU_DONE = BIT(31),
55 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an
56 * A-MPDU shall have both first_mpdu and last_mpdu bits set to
57 * 0. The PPDU start status will only be valid when this bit
62 * PPDU end status will only be valid when this bit is set.
66 * address 1 bit 0 is set indicating mcast/bcast and the BSSID
79 * Power management bit set in the 802.11 header. Only set
83 * Set if packet is not a non-QoS data frame. Only set when
99 * Set if more bit in frame control is set. Only set when
103 * Set if the EOSP (end of service period) bit in the QoS
107 * Set if packet is U-APSD trigger. Key table will have bits
108 * per TID to indicate U-APSD trigger.
112 * set when either the more_frag bit is set in the frame
117 * Set if the order bit in the frame control is set. Only set
170 * 'no_ack' bit is the address search entry cleared.
178 * Indicates that the MPDU was pre-maturely terminated
195 * valid. This bit must be in the last octet of the
235 * ring 2. Field is filled in by the RX_DMA.
245 HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC = 2,
262 #define RX_MPDU_START_INFO0_FROM_DS BIT(11)
263 #define RX_MPDU_START_INFO0_TO_DS BIT(12)
264 #define RX_MPDU_START_INFO0_ENCRYPTED BIT(13)
265 #define RX_MPDU_START_INFO0_RETRY BIT(14)
266 #define RX_MPDU_START_INFO0_TXBF_H_INFO BIT(15)
270 #define RX_MPDU_START_INFO1_DIRECTED BIT(16)
292 * Set if the from DS bit is set in the frame control. Only
296 * Set if the to DS bit is set in the frame control. Only
300 * Protected bit from the frame control. Only valid when
304 * Retry bit from the frame control. Only valid when
320 * 2: TKIP without MIC
324 * 6: AES-CCM (WPA2)
334 * AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1,
349 * byte-order and bitmasking/bitshifting.
365 #define RX_MPDU_END_INFO0_OVERFLOW_ERR BIT(13)
366 #define RX_MPDU_END_INFO0_LAST_MPDU BIT(14)
367 #define RX_MPDU_END_INFO0_POST_DELIM_ERR BIT(15)
368 #define RX_MPDU_END_INFO0_MPDU_LENGTH_ERR BIT(28)
369 #define RX_MPDU_END_INFO0_TKIP_MIC_ERR BIT(29)
370 #define RX_MPDU_END_INFO0_DECRYPT_ERR BIT(30)
371 #define RX_MPDU_END_INFO0_FCS_ERR BIT(31)
400 * ML-MIMO is used. Only valid when last_mpdu is set.
430 #define RX_MSDU_START_INFO1_IPV4_PROTO BIT(10)
431 #define RX_MSDU_START_INFO1_IPV6_PROTO BIT(11)
432 #define RX_MSDU_START_INFO1_TCP_PROTO BIT(12)
433 #define RX_MSDU_START_INFO1_UDP_PROTO BIT(13)
434 #define RX_MSDU_START_INFO1_IP_FRAG BIT(14)
435 #define RX_MSDU_START_INFO1_TCP_ONLY_ACK BIT(15)
441 #define RX_MSDU_START_INFO2_DA_BCAST_MCAST BIT(11)
447 * - 0 bytes for no security
448 * - 4 bytes for WEP
449 * - 8 bytes for TKIP, AES
451 * c) A-MSDU subframe header (14 bytes) if applicable
454 * In case of A-MSDU only first frame in sequence contains (a) and (b).
459 /* Note: QoS frames are reported as non-QoS. The rx_hdr_status in
465 RX_MSDU_DECAP_ETHERNET2_DIX = 2,
467 /* Payload contains two 48-bit addresses and 2-byte length (14 bytes
505 * still valid for MPDU frames without A-MSDU. It still
534 * {16'b0, urgent_ptr[15:0]}, all options except 32-bit
546 * 2: Ethernet 2 (DIX)
564 * Indicates that either the IP More frag bit is set or IP frag
565 * number is non-zero. If set indicates that this is a
569 * Set if only the TCP Ack bit is set in the TCP flags and if
582 #define RX_MSDU_END_INFO0_FIRST_MSDU BIT(14)
583 #define RX_MSDU_END_INFO0_LAST_MSDU BIT(15)
584 #define RX_MSDU_END_INFO0_MSDU_LIMIT_ERR BIT(18)
585 #define RX_MSDU_END_INFO0_PRE_DELIM_ERR BIT(30)
586 #define RX_MSDU_END_INFO0_RESERVED_3B BIT(31)
603 #define RX_MSDU_END_INFO1_IRO_ELIGIBLE BIT(9)
652 * The value of the computed TCP/UDP checksum. A mode bit
682 * length field of the A-MPDU delimiter or the preamble length
683 * field for non-A-MPDU frames.
686 * Indicates the first MSDU of A-MSDU. If both first_msdu and
687 * last_msdu are set in the MSDU then this is a non-aggregated
688 * MSDU frame: normal MPDU. Interior MSDU in an A-MSDU shall
692 * Indicates the last MSDU of the A-MSDU. MPDU end status is
718 #define RX_PPDU_START_INFO0_IS_GREENFIELD BIT(0)
728 #define RX_PPDU_START_INFO1_L_SIG_RATE_SELECT BIT(4)
729 #define RX_PPDU_START_INFO1_L_SIG_PARITY BIT(17)
736 #define RX_PPDU_START_INFO3_TXBF_H_INFO BIT(24)
745 #define RX_PPDU_START_RATE_FLAG BIT(3)
798 * RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth.
802 * RSSI of RX PPDU on chain 2 of secondary 20 MHz bandwidth.
806 * RSSI of RX PPDU on chain 2 of secondary 40 MHz bandwidth.
810 * RSSI of RX PPDU on chain 2 of secondary 80 MHz bandwidth.
855 * 0xA: CCK 2 Mbps long preamble
859 * 0xE: CCK 2 Mbps short preamble
881 * 0x80 - 0xFF: Reserved for special baseband data types such
886 * HT-SIG (first 24 bits)
888 * VHT-SIG A (first 24 bits)
897 * HT-SIG (last 24 bits)
899 * VHT-SIG A (last 24 bits)
912 * 0s since the BB does not plan on decoding VHT SIG-B.
925 #define RX_PPDU_END_FLAGS_PHY_ERR BIT(0)
926 #define RX_PPDU_END_FLAGS_RX_LOCATION BIT(1)
927 #define RX_PPDU_END_FLAGS_TXBF_H_INFO BIT(2)
931 #define RX_PPDU_END_INFO0_FLAGS_TX_HT_VHT_ACK BIT(24)
932 #define RX_PPDU_END_INFO0_BB_CAPTURED_CHANNEL BIT(25)
935 #define RX_PPDU_END_INFO1_PEER_IDX_LSB 2
936 #define RX_PPDU_END_INFO1_BB_DATA BIT(0)
937 #define RX_PPDU_END_INFO1_PEER_IDX_VALID BIT(1)
938 #define RX_PPDU_END_INFO1_PPDU_DONE BIT(15)
974 #define RX_PPDU_END_RTT_NORMAL_MODE BIT(31)
986 #define RX_PKT_END_INFO0_RX_SUCCESS BIT(0)
987 #define RX_PKT_END_INFO0_ERR_TX_INTERRUPT_RX BIT(3)
988 #define RX_PKT_END_INFO0_ERR_OFDM_POWER_DROP BIT(4)
989 #define RX_PKT_END_INFO0_ERR_OFDM_RESTART BIT(5)
990 #define RX_PKT_END_INFO0_ERR_CCK_POWER_DROP BIT(6)
991 #define RX_PKT_END_INFO0_ERR_CCK_RESTART BIT(7)
1001 #define RX_LOCATION_INFO_CIR_STATUS BIT(17)
1002 #define RX_LOCATION_INFO_RTT_MAC_PHY_PHASE BIT(25)
1003 #define RX_LOCATION_INFO_RTT_TX_DATA_START_X BIT(26)
1004 #define RX_LOCATION_INFO_HW_IFFT_MODE BIT(30)
1005 #define RX_LOCATION_INFO_RX_LOCATION_VALID BIT(31)
1025 #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_STATUS BIT(14)
1026 #define RX_LOCATION_INFO0_RTT_FAC_VHT_STATUS BIT(29)
1029 #define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_LSB 2
1042 #define RX_LOCATION_INFO1_RTT_CFR_STATUS BIT(0)
1043 #define RX_LOCATION_INFO1_RTT_CIR_STATUS BIT(1)
1044 #define RX_LOCATION_INFO1_RTT_GI_TYPE BIT(7)
1045 #define RX_LOCATION_INFO1_RTT_MAC_PHY_PHASE BIT(29)
1046 #define RX_LOCATION_INFO1_RTT_TX_DATA_START_X_PHASE BIT(30)
1047 #define RX_LOCATION_INFO1_RX_LOCATION_VALID BIT(31)
1061 RX_PHY_PPDU_END_INFO0_ERR_RADAR = BIT(2),
1062 RX_PHY_PPDU_END_INFO0_ERR_RX_ABORT = BIT(3),
1063 RX_PHY_PPDU_END_INFO0_ERR_RX_NAP = BIT(4),
1064 RX_PHY_PPDU_END_INFO0_ERR_OFDM_TIMING = BIT(5),
1065 RX_PHY_PPDU_END_INFO0_ERR_OFDM_PARITY = BIT(6),
1066 RX_PHY_PPDU_END_INFO0_ERR_OFDM_RATE = BIT(7),
1067 RX_PHY_PPDU_END_INFO0_ERR_OFDM_LENGTH = BIT(8),
1068 RX_PHY_PPDU_END_INFO0_ERR_OFDM_RESTART = BIT(9),
1069 RX_PHY_PPDU_END_INFO0_ERR_OFDM_SERVICE = BIT(10),
1070 RX_PHY_PPDU_END_INFO0_ERR_OFDM_POWER_DROP = BIT(11),
1071 RX_PHY_PPDU_END_INFO0_ERR_CCK_BLOCKER = BIT(12),
1072 RX_PHY_PPDU_END_INFO0_ERR_CCK_TIMING = BIT(13),
1073 RX_PHY_PPDU_END_INFO0_ERR_CCK_HEADER_CRC = BIT(14),
1074 RX_PHY_PPDU_END_INFO0_ERR_CCK_RATE = BIT(15),
1075 RX_PHY_PPDU_END_INFO0_ERR_CCK_LENGTH = BIT(16),
1076 RX_PHY_PPDU_END_INFO0_ERR_CCK_RESTART = BIT(17),
1077 RX_PHY_PPDU_END_INFO0_ERR_CCK_SERVICE = BIT(18),
1078 RX_PHY_PPDU_END_INFO0_ERR_CCK_POWER_DROP = BIT(19),
1079 RX_PHY_PPDU_END_INFO0_ERR_HT_CRC = BIT(20),
1080 RX_PHY_PPDU_END_INFO0_ERR_HT_LENGTH = BIT(21),
1081 RX_PHY_PPDU_END_INFO0_ERR_HT_RATE = BIT(22),
1082 RX_PHY_PPDU_END_INFO0_ERR_HT_ZLF = BIT(23),
1083 RX_PHY_PPDU_END_INFO0_ERR_FALSE_RADAR_EXT = BIT(24),
1084 RX_PHY_PPDU_END_INFO0_ERR_GREEN_FIELD = BIT(25),
1085 RX_PHY_PPDU_END_INFO0_ERR_SPECTRAL_SCAN = BIT(26),
1086 RX_PHY_PPDU_END_INFO0_ERR_RX_DYN_BW = BIT(27),
1087 RX_PHY_PPDU_END_INFO0_ERR_LEG_HT_MISMATCH = BIT(28),
1088 RX_PHY_PPDU_END_INFO0_ERR_VHT_CRC = BIT(29),
1089 RX_PHY_PPDU_END_INFO0_ERR_VHT_SIGA = BIT(30),
1090 RX_PHY_PPDU_END_INFO0_ERR_VHT_LSIG = BIT(31),
1094 RX_PHY_PPDU_END_INFO1_ERR_VHT_NDP = BIT(0),
1095 RX_PHY_PPDU_END_INFO1_ERR_VHT_NSYM = BIT(1),
1096 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_EXT_SYM = BIT(2),
1097 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID0 = BIT(3),
1098 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID1_62 = BIT(4),
1099 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID63 = BIT(5),
1100 RX_PHY_PPDU_END_INFO1_ERR_OFDM_LDPC_DECODER = BIT(6),
1101 RX_PHY_PPDU_END_INFO1_ERR_DEFER_NAP = BIT(7),
1102 RX_PHY_PPDU_END_INFO1_ERR_FDOMAIN_TIMEOUT = BIT(8),
1103 RX_PHY_PPDU_END_INFO1_ERR_LSIG_REL_CHECK = BIT(9),
1104 RX_PHY_PPDU_END_INFO1_ERR_BT_COLLISION = BIT(10),
1105 RX_PHY_PPDU_END_INFO1_ERR_MU_FEEDBACK = BIT(11),
1106 RX_PHY_PPDU_END_INFO1_ERR_TX_INTERRUPT_RX = BIT(12),
1107 RX_PHY_PPDU_END_INFO1_ERR_RX_CBF = BIT(13),
1120 #define RX_PPDU_END_RX_INFO_TX_HT_VHT_ACK BIT(24)
1121 #define RX_PPDU_END_RX_INFO_RX_PKT_END_VALID BIT(25)
1122 #define RX_PPDU_END_RX_INFO_RX_PHY_PPDU_END_VALID BIT(26)
1123 #define RX_PPDU_END_RX_INFO_RX_TIMING_OFFSET_VALID BIT(27)
1124 #define RX_PPDU_END_RX_INFO_BB_CAPTURED_CHANNEL BIT(28)
1125 #define RX_PPDU_END_RX_INFO_UNSUPPORTED_MU_NC BIT(29)
1126 #define RX_PPDU_END_RX_INFO_OTP_TXBF_DISABLE BIT(30)
1181 * EVM for pilot 0. Contain EVM for streams: 0, 1, 2 and 3.
1184 * EVM for pilot 1. Contain EVM for streams: 0, 1, 2 and 3.
1187 * EVM for pilot 2. Contain EVM for streams: 0, 1, 2 and 3.
1190 * EVM for pilot 3. Contain EVM for streams: 0, 1, 2 and 3.
1193 * EVM for pilot 4. Contain EVM for streams: 0, 1, 2 and 3.
1196 * EVM for pilot 5. Contain EVM for streams: 0, 1, 2 and 3.
1199 * EVM for pilot 6. Contain EVM for streams: 0, 1, 2 and 3.
1202 * EVM for pilot 7. Contain EVM for streams: 0, 1, 2 and 3.
1205 * EVM for pilot 8. Contain EVM for streams: 0, 1, 2 and 3.
1208 * EVM for pilot 9. Contain EVM for streams: 0, 1, 2 and 3.
1211 * EVM for pilot 10. Contain EVM for streams: 0, 1, 2 and 3.
1214 * EVM for pilot 11. Contain EVM for streams: 0, 1, 2 and 3.
1217 * EVM for pilot 12. Contain EVM for streams: 0, 1, 2 and 3.
1220 * EVM for pilot 13. Contain EVM for streams: 0, 1, 2 and 3.
1223 * EVM for pilot 14. Contain EVM for streams: 0, 1, 2 and 3.
1226 * EVM for pilot 15. Contain EVM for streams: 0, 1, 2 and 3.
1250 * See the 1.10.8.1.2 for the list of the PHY error codes.
1276 * capture_channel bit BB descriptor or FW setting the
1277 * capture_channel mode bit.
1292 * PPDU end status is only valid when ppdu_done bit is set.
1293 * Every time HW sets this bit in memory FW/SW must clear this
1294 * bit in memory. FW will initialize all the ppdu_done dword
1298 #define FW_RX_DESC_INFO0_DISCARD BIT(0)
1299 #define FW_RX_DESC_INFO0_FORWARD BIT(1)
1300 #define FW_RX_DESC_INFO0_INSPECT BIT(5)
1310 #define FW_RX_DESC_C3_FAILED (1 << 2)
1325 extension:2;