Lines Matching +full:2 +full:- +full:bit
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
16 * 2. Redistributions in binary form must reproduce the above copyright
37 #define BIT(n) (1ULL << (n)) macro
38 /* Return value of bits[n:m] where n and (n >= ) m are bit positions. */
40 ((1 << (((n) - (m)) + 1)) - 1))
45 #define AMDVI_PCI_CAP_IOTLB BIT(0) /* IOTLB is supported. */
46 #define AMDVI_PCI_CAP_HT BIT(1) /* HyperTransport tunnel support. */
47 #define AMDVI_PCI_CAP_NPCACHE BIT(2) /* Not present page cached. */
48 #define AMDVI_PCI_CAP_EFR BIT(3) /* Extended features. */
49 #define AMDVI_PCI_CAP_EXT BIT(4) /* Miscellaneous information reg. */
54 #define AMDVI_EX_FEA_PREFSUP BIT(0) /* Prefetch command support. */
55 #define AMDVI_EX_FEA_PPRSUP BIT(1) /* PPR support */
56 #define AMDVI_EX_FEA_XTSUP BIT(2) /* Reserved */
57 #define AMDVI_EX_FEA_NXSUP BIT(3) /* No-execute. */
58 #define AMDVI_EX_FEA_GTSUP BIT(4) /* Guest translation support. */
59 #define AMDVI_EX_FEA_EFRW BIT(5) /* Reserved */
60 #define AMDVI_EX_FEA_IASUP BIT(6) /* Invalidate all command supp. */
61 #define AMDVI_EX_FEA_GASUP BIT(7) /* Guest APIC or AVIC support. */
62 #define AMDVI_EX_FEA_HESUP BIT(8) /* Hardware Error. */
63 #define AMDVI_EX_FEA_PCSUP BIT(9) /* Performance counters support. */
68 * NOTE: Must be 256-bits/32 bytes aligned.
73 uint16_t :7; /* Reserved[8:2] */
77 uint8_t gv_valid:1; /* Revision 2, GVA to SPA. */
78 uint8_t gv_level:2; /* Revision 2, GLX level. */
79 uint8_t gv_cr3_lsb:3; /* Revision 2, GCR3[14:12] */
84 uint16_t gv_cr3_lsb2:16; /* Revision 2, GCR3[30:15] */
88 uint8_t IOctl:2; /* Port I/O control. */
92 uint8_t sysmgmt:2; /* System management message.*/
94 uint32_t gv_cr3_msb:21; /* Revision 2, GCR3[51:31] */
104 uint8_t intr_ctrl:2; /* Interrupt control */
132 #define AMDVI_CMP_WAIT_STORE BIT(0) /* Write back data. */
133 #define AMDVI_CMP_WAIT_INTR BIT(1) /* Completion wait interrupt. */
134 #define AMDVI_CMP_WAIT_FLUSH BIT(2) /* Flush queue. */
137 #define AMDVI_INVD_PAGE_S BIT(0) /* Invalidation size. */
138 #define AMDVI_INVD_PAGE_PDE BIT(1) /* Invalidate PDE. */
139 #define AMDVI_INVD_PAGE_GN_GVA BIT(2) /* GPA or GVA. */
144 #define AMDVI_INVD_IOTLB_S BIT(0) /* Invalidation size 4k or addr */
145 #define AMDVI_INVD_IOTLB_GN_GVA BIT(2) /* GPA or GVA. */
215 * Revision 2 only.
228 /* Revision 2 only, end. */
265 #define IVHD_FLAG_HTT BIT(0) /* Hypertransport Tunnel. */
266 #define IVHD_FLAG_PPW BIT(1) /* Pass posted write. */
267 #define IVHD_FLAG_RPPW BIT(2) /* Response pass posted write. */
268 #define IVHD_FLAG_ISOC BIT(3) /* Isoc support. */
269 #define IVHD_FLAG_IOTLB BIT(4) /* IOTLB support. */
270 #define IVHD_FLAG_COH BIT(5) /* Coherent control, default 1 */
271 #define IVHD_FLAG_PFS BIT(6) /* Prefetch IOMMU pages. */
272 #define IVHD_FLAG_PPRS BIT(7) /* Peripheral page support. */
275 #define IVHD_DEV_LINT0_PASS BIT(6) /* LINT0 interrupts. */
276 #define IVHD_DEV_LINT1_PASS BIT(7) /* LINT1 interrupts. */
278 /* Bit[5:4] for System Mgmt. Bit3 is reserved. */
279 #define IVHD_DEV_INIT_PASS BIT(0) /* INIT */
280 #define IVHD_DEV_EXTINTR_PASS BIT(1) /* ExtInt */
281 #define IVHD_DEV_NMI_PASS BIT(2) /* NMI */
283 /* IVHD 8-byte extended data settings. */
284 #define IVHD_DEV_EXT_ATS_DISABLE BIT(31) /* Disable ATS */
287 #define AMDVI_CTRL_EN BIT(0) /* IOMMU enable. */
288 #define AMDVI_CTRL_HTT BIT(1) /* Hypertransport tunnel enable. */
289 #define AMDVI_CTRL_ELOG BIT(2) /* Event log enable. */
290 #define AMDVI_CTRL_ELOGINT BIT(3) /* Event log interrupt. */
291 #define AMDVI_CTRL_COMINT BIT(4) /* Completion wait interrupt. */
292 #define AMDVI_CTRL_PPW BIT(8)
293 #define AMDVI_CTRL_RPPW BIT(9)
294 #define AMDVI_CTRL_COH BIT(10)
295 #define AMDVI_CTRL_ISOC BIT(11)
296 #define AMDVI_CTRL_CMD BIT(12) /* Command buffer enable. */
297 #define AMDVI_CTRL_PPRLOG BIT(13)
298 #define AMDVI_CTRL_PPRINT BIT(14)
299 #define AMDVI_CTRL_PPREN BIT(15)
300 #define AMDVI_CTRL_GTE BIT(16) /* Guest translation enable. */
301 #define AMDVI_CTRL_GAE BIT(17) /* Guest APIC enable. */
306 #define AMDVI_CTRL_INV_TO_10ms 2 /* 10 ms */
319 #define AMDVI_MAX_DOMAIN (BIT(16) - 1)
324 #define AMDVI_PT_PRESENT BIT(0)
325 #define AMDVI_PT_COHERENT BIT(60)
326 #define AMDVI_PT_READ BIT(61)
327 #define AMDVI_PT_WRITE BIT(62)
337 #define AMDVI_STATUS_EV_OF BIT(0) /* Event overflow. */
338 #define AMDVI_STATUS_EV_INTR BIT(1) /* Event interrupt. */
340 #define AMDVI_STATUS_CMP BIT(2)