Lines Matching +full:2 +full:- +full:bit
1 /* SPDX-License-Identifier: BSD-3-Clause */
11 * 2. Redistributions in binary form must reproduce the above copyright
87 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
105 #define ICE_AQC_RES_ID_SDP 2
110 #define ICE_AQC_RES_ACCESS_WRITE 2
127 #define ICE_AQ_RES_GLBL_DONE 2
128 u8 reserved[2];
137 u8 reserved[2];
203 /* Manage MAC address, read command - indirect (0x0107)
208 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
209 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
210 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
211 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
212 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8)
213 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9)
216 u8 rsvd[2];
232 /* Manage MAC address, write command - direct (0x0108) */
236 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
237 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
241 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
255 /* Configure No-Drop Policy Command (direct 0x0112) */
258 #define ICE_AQC_FORCE_NO_DROP BIT(0)
290 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
295 /* Bit 14..0 : PF/VF number VSI belongs to
296 * Bit 15 : VF indication bit
302 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
308 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0)
309 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1)
310 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2)
314 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15)
321 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14)
322 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15)
324 #define ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_VALID BIT(2)
362 /* Resource types 0x62-67 are reserved for Hash profile builder */
366 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
367 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
368 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
369 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_SHARED BIT(14)
370 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_CTL BIT(15)
391 __le16 total_free; /* Resources un-allocated/not reserved by any PF */
460 u8 rdma_reserved[2];
470 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0)
484 #define ICE_AQ_VSI_IS_VALID BIT(15)
529 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
530 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
531 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
532 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
533 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
534 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
535 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
536 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
537 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
538 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
539 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
543 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
544 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
545 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
549 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
550 #define ICE_AQ_VSI_SW_FLAG_RX_PASS_PRUNE_ENA BIT(3)
551 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
555 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
558 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
559 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
562 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
566 u8 inner_vlan_reserved[2];
573 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2)
580 #define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5)
610 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
616 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4)
622 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7)
627 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
643 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
654 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
656 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
664 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
665 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
666 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
679 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
684 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
688 /* Add/update mirror rule - direct (0x0260) */
697 /* Action: Byte.bit (1.7)
708 * In case of add mirror rule - if rule ID is specified as
742 /* Delete mirror rule - direct(0x0261) */
747 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of
758 /* Set/Get storm config - (direct 0x0280, 0x0281) */
765 /* Bit 18:0 - Traffic upper threshold size
766 * Bit 31:19 - Reserved
772 /* Bit 0: MDIPW - Drop Multicast packets in previous window
773 * Bit 1: MDICW - Drop multicast packets in current window
774 * Bit 2: BDIPW - Drop broadcast packets in previous window
775 * Bit 3: BDICW - Drop broadcast packets in current window
777 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0)
778 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1)
779 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2)
780 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3)
781 /* Bit 7:5 : Reserved */
782 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The
838 /* Bit 0:1 - Action type */
842 /* Bit 2 - Loop back enable
843 * Bit 3 - LAN enable
845 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
846 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
848 /* Action type = 0 - Forward to VSI or VSI list */
855 /* This bit needs to be set if action is forward to VSI list */
856 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
857 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
858 #define ICE_SINGLE_ACT_DROP BIT(18)
860 /* Action type = 1 - Forward to Queue of Queue group */
866 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
868 /* Action type = 2 - Prune */
870 #define ICE_SINGLE_ACT_EGRESS BIT(15)
871 #define ICE_SINGLE_ACT_INGRESS BIT(16)
872 #define ICE_SINGLE_ACT_PRUNET BIT(17)
873 /* Bit 18 should be set to 0 for this action */
875 /* Action type = 2 - Pointer */
879 /* Bit 17 should be set if pointed action includes a FWD cmd */
880 #define ICE_SINGLE_ACT_PTR_HAS_FWD BIT(17)
881 /* Bit 18 should be set to 1 */
882 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
884 /* Action type = 3 - Other actions. Last two bits
892 /* Bit 17:18 - Defines other actions */
893 /* Other action = 0 - Mirror VSI */
899 /* Other action = 3 - Set Stat count */
907 * lookup-type
925 /* Bit 0:1 - Action type */
929 /* Action type = 0 - Forward to VSI or VSI list */
935 /* This bit needs to be set if action is forward to VSI list */
936 #define ICE_LG_ACT_VSI_LIST BIT(13)
938 #define ICE_LG_ACT_VALID_BIT BIT(16)
940 /* Action type = 1 - Forward to Queue of Queue group */
946 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
948 /* Action type = 2 - Prune */
950 #define ICE_LG_ACT_EGRESS BIT(14)
951 #define ICE_LG_ACT_INGRESS BIT(15)
952 #define ICE_LG_ACT_PRUNET BIT(16)
954 /* Action type = 3 - Mirror VSI */
959 /* Action type = 5 - Generic Value */
969 /* Action = 7 - Set Stat count */
1005 #define ICE_AQC_PFC_IGNORE_SET BIT(7)
1020 #define ICE_AQC_PFC_DSCP_BASED_PFC 2
1027 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0)
1028 #define ICE_AQC_PERSIST_DCB_CFG BIT(1)
1030 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0)
1031 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1)
1048 #define ICE_AQC_TX_TOPO_FLAGS_CORRER BIT(0)
1049 #define ICE_AQC_TX_TOPO_FLAGS_SRC_RAM BIT(1)
1050 #define ICE_AQC_TX_TOPO_FLAGS_SET_PSM BIT(2)
1051 #define ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW BIT(4)
1052 #define ICE_AQC_TX_TOPO_FLAGS_ISSUED BIT(5)
1056 #define ICE_AQC_TX_TOPO_GET_RAM 2
1107 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
1108 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
1109 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
1110 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
1170 /* 3 bits for UP per TC 0-7, 4th byte reserved */
1175 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
1204 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
1303 /* 18.0 - Report qualified modules */
1304 #define ICE_AQC_GET_PHY_RQM BIT(0)
1305 /* 18.1 - 18.3 : Report mode
1306 * 000b - Report topology capabilities, without media
1307 * 001b - Report topology capabilities, with media
1308 * 010b - Report Active configuration
1309 * 011b - Report PHY Type and FEC mode capabilities
1310 * 100b - Report Default capabilities
1315 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1)
1316 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2)
1317 #define ICE_AQC_REPORT_DFLT_CFG BIT(3)
1328 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1394 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1414 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1415 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1416 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1417 #define ICE_AQC_PHY_EN_LINK BIT(3)
1418 #define ICE_AQC_PHY_AN_MODE BIT(4)
1419 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5)
1420 #define ICE_AQC_PHY_EN_LESM BIT(6)
1421 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1424 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1425 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
1426 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
1427 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
1429 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1430 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1431 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1432 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1433 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1434 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1435 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1436 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7)
1437 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8)
1438 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9)
1439 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10)
1444 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1445 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1446 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1447 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1448 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1449 #define ICE_AQC_PHY_FEC_DIS BIT(5)
1450 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1451 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1454 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
1461 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1462 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1463 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1464 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1465 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1466 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1482 * NOTE: This command must be followed by setup link and restart auto-neg
1497 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1498 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1499 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1500 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1501 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1502 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1503 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1517 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1524 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1526 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1537 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1538 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1560 ICE_GET_LINK_STATUS_DATA_V2 = 2,
1570 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1571 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1572 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1573 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1574 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1575 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1576 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1578 #define ICE_AQ_LINK_CFG_ERR BIT(0)
1579 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2)
1580 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3)
1581 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4)
1582 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5)
1583 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6)
1584 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7)
1586 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1587 #define ICE_AQ_LINK_FAULT BIT(1)
1588 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1589 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1590 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1591 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1592 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1593 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1595 #define ICE_AQ_AN_COMPLETED BIT(0)
1596 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1597 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1598 #define ICE_AQ_FEC_EN BIT(3)
1599 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1600 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1601 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1602 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1604 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1605 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1607 #define ICE_AQ_LINK_TX_S 2
1613 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0)
1614 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1)
1615 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2)
1620 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1621 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1622 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1627 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1637 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1641 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1642 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1643 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1644 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1645 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1646 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1647 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1648 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1649 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1650 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1651 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1652 #define ICE_AQ_LINK_SPEED_200GB BIT(11)
1653 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1654 __le16 reserved3; /* Aligns next field to 8-byte boundary */
1656 #define ICE_AQ_LINK_RS_272_FEC_EN BIT(0) /* RS 272 FEC enabled */
1660 /* Get link status version 2 link partner data */
1664 #define ICE_AQ_LINK_LP_10G_KR_FEC_CAP BIT(0)
1665 #define ICE_AQ_LINK_LP_25G_KR_FEC_CAP BIT(1)
1666 #define ICE_AQ_LINK_LP_RS_528_FEC_CAP BIT(2)
1667 #define ICE_AQ_LINK_LP_50G_KR_272_FEC_CAP BIT(3)
1668 #define ICE_AQ_LINK_LP_100G_KR_272_FEC_CAP BIT(4)
1669 #define ICE_AQ_LINK_LP_200G_KR_272_FEC_CAP BIT(5)
1671 #define ICE_AQ_LINK_LP_10G_KR_FEC_REQ BIT(0)
1672 #define ICE_AQ_LINK_LP_25G_KR_FEC_REQ BIT(1)
1673 #define ICE_AQ_LINK_LP_RS_528_FEC_REQ BIT(2)
1674 #define ICE_AQ_LINK_LP_KR_272_FEC_REQ BIT(3)
1676 #define ICE_AQ_LINK_LP_PAUSE_ADV BIT(0)
1677 #define ICE_AQ_LINK_LP_ASM_DIR_ADV BIT(1)
1688 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1689 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1690 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1691 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1692 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1693 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1694 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1695 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1696 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1697 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10)
1698 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11)
1699 #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12)
1707 #define ICE_AQ_PHY_LB_PORT_NUM_VALID BIT(0)
1710 #define ICE_AQ_PHY_LB_EN BIT(0)
1711 #define ICE_AQ_PHY_LB_TYPE_M BIT(1)
1714 #define ICE_AQ_PHY_LB_LEVEL_M BIT(2)
1723 #define ICE_AQ_MAC_LB_EN BIT(0)
1724 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1773 #define ICE_AQ_DNL_FLAGS_ERROR BIT(2)
1774 #define ICE_AQ_DNL_FLAGS_NEGATIVE BIT(3)
1775 #define ICE_AQ_DNL_FLAGS_OVERFLOW BIT(4)
1776 #define ICE_AQ_DNL_FLAGS_ZERO BIT(5)
1777 #define ICE_AQ_DNL_FLAGS_CARRY BIT(6)
1778 #define ICE_AQ_DNL_FLAGS_JUMP BIT(7)
1868 /* Equalization value can be -ve */
1913 __le32 reserved[2];
1921 u8 ena; /* 0- disabled, 1- enabled */
1949 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
1955 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
1967 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
1980 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
1982 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ BIT(9)
2009 #define ICE_AQC_I2C_ADDR_TYPE_M BIT(4)
2014 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7)
2033 #define ICE_AQC_MDIO_CLAUSE_22 BIT(5)
2034 #define ICE_AQC_MDIO_CLAUSE_45 BIT(6)
2050 #define ICE_AQC_GPIO_ON BIT(0)
2063 #define ICE_AQC_LED_COLOR_ORANGE 2
2072 #define ICE_AQC_LED_BLINK_SLOW_MAC 2
2084 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0)
2086 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
2095 #define ICE_AQC_PORT_OPT_PORT_NUM_VALID BIT(0)
2104 #define ICE_AQC_PORT_OPT_FORCED BIT(6)
2105 #define ICE_AQC_PORT_OPT_VALID BIT(7)
2109 #define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7)
2110 u8 rsvd[2];
2127 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2
2134 u8 global_scid[2];
2135 u8 phy_scid[2];
2136 u8 pf2port_cid[2];
2143 #define ICE_AQC_SET_PORT_OPT_PORT_NUM_VALID BIT(0)
2162 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
2166 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
2173 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
2174 #define ICE_AQC_SFF_IS_WRITE BIT(15)
2196 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1)
2197 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0)
2226 #define ICE_AQC_NVM_LAST_CMD BIT(0)
2227 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */
2231 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
2232 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
2234 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
2235 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
2236 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
2237 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
2238 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
2240 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
2244 #define ICE_AQC_NVM_EMPR_FLAG 2
2245 #define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */
2248 * interface, we pass the flags as a 16 bit value so these flags are
2251 #define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */
2261 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */
2265 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */
2268 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15)
2272 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */
2273 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */
2276 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */
2282 #define ICE_AQC_NVM_SDP_CFG_PTR_RD_LEN 2 /* In Bytes */
2284 #define ICE_AQC_NVM_SDP_CFG_PTR_TYPE_M BIT(15)
2285 #define ICE_AQC_NVM_SDP_CFG_HEADER_LEN 2 /* In Bytes */
2286 #define ICE_AQC_NVM_SDP_CFG_SEC_LEN_LEN 2 /* In Bytes */
2311 #define ICE_AQC_NVM_CMPO_ENABLE BIT(8)
2322 #define ICE_AQC_NVM_MINSREV_NVM_VALID BIT(0)
2323 #define ICE_AQC_NVM_MINSREV_OROM_VALID BIT(1)
2333 #define ICE_AQC_NVM_TX_TOPO_USER_SEL BIT(4)
2340 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
2341 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)
2342 #define ICE_AQC_ANVM_NEW_CFG BIT(2)
2346 u8 reserved1[2];
2360 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
2361 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
2368 /* Used for NVM Sanitization command - 0x070C */
2372 #define ICE_AQ_NVM_SANITIZE_REQ_OPERATE BIT(0)
2375 #define ICE_AQ_NVM_SANITIZE_READ_SUBJECT_NVM_STATE BIT(1)
2378 #define ICE_AQ_NVM_SANITIZE_NVM_BITS_HOST_CLEAN_SUPPORT BIT(0)
2379 #define ICE_AQ_NVM_SANITIZE_NVM_BITS_BMC_CLEAN_SUPPORT BIT(2)
2380 #define ICE_AQ_NVM_SANITIZE_NVM_STATE_HOST_CLEAN_DONE BIT(0)
2381 #define ICE_AQ_NVM_SANITIZE_NVM_STATE_HOST_CLEAN_SUCCESS BIT(1)
2382 #define ICE_AQ_NVM_SANITIZE_NVM_STATE_BMC_CLEAN_DONE BIT(2)
2383 #define ICE_AQ_NVM_SANITIZE_NVM_STATE_BMC_CLEAN_SUCCESS BIT(3)
2384 #define ICE_AQ_NVM_SANITIZE_OPERATE_HOST_CLEAN_DONE BIT(0)
2385 #define ICE_AQ_NVM_SANITIZE_OPERATE_HOST_CLEAN_SUCCESS BIT(1)
2386 #define ICE_AQ_NVM_SANITIZE_OPERATE_BMC_CLEAN_DONE BIT(2)
2387 #define ICE_AQ_NVM_SANITIZE_OPERATE_BMC_CLEAN_SUCCESS BIT(3)
2404 /* Write/Read Alternate - Direct (direct 0x0900/0x0902) */
2412 /* Write/Read Alternate - Indirect (indirect 0x0901/0x0903) */
2423 #define ICE_AQC_CMD_UEFI_BIOS_MODE BIT(0)
2424 #define ICE_AQC_RESP_RESET_NEEDED BIT(1)
2443 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
2444 #define ICE_AQ_LLDP_BRID_TYPE_S 2
2459 #define ICE_AQ_LLDP_DCBX_IEEE 2
2472 u8 reserved[2];
2495 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2505 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2517 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
2520 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
2527 #define ICE_AQ_LLDP_AGENT_START BIT(0)
2528 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
2567 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
2569 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
2581 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0)
2594 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
2614 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
2630 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer
2647 ICE_LUT_GLOBAL = 2,
2661 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
2669 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
2674 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
2709 u8 rsvd[2];
2712 u8 rsvd2[2];
2734 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
2735 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
2737 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
2738 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
2754 * number of queues is even, then 2 bytes of alignment MUST be
2786 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2
2788 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2)
2789 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3)
2793 #define ICE_AQC_Q_CMD_TIMEOUT_S 2
2800 /* Per-queue data buffer for the Move Tx LAN Queues command/response */
2828 u8 rsvd[2];
2841 u8 rsvd[2];
2926 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0)
2931 u8 rsvd[2];
2949 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED_E810 2
2974 __le16 table_id; /* Used only for non-memory clusters */
3019 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0)
3020 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1)
3021 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2)
3110 #define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0)
3111 #define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1)
3112 #define ICE_AQC_FW_LOG_QUERY_REGISTERED BIT(2)
3113 #define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3)
3114 #define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0)
3115 #define ICE_AQC_FW_LOG_AQ_QUERY BIT(2)
3116 #define ICE_AQC_FW_LOG_PERSISTENT BIT(0)
3118 #define ICE_AQC_FW_LOG_MORE_DATA BIT(1)
3146 * struct ice_aq_desc - Admin Queue (AQ) descriptor
3151 * @cookie_high: opaque data high-half
3152 * @cookie_low: opaque data low-half
3153 * @params: command-specific parameters
3159 * the same descriptor format. Descriptors are in little-endian notation with
3160 * 32-bit words.
3284 /* Flags sub-structure
3285 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
3292 #define ICE_AQ_FLAG_ERR_S 2
3302 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
3303 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
3304 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
3305 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */
3306 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
3307 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
3308 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */
3309 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
3310 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
3311 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */
3312 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */
3318 ICE_AQ_RC_ENOENT = 2, /* No such element */
3339 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */
3391 /* Mirroring rules - add/update, delete */