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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchFixupKinds.h26 // 16-bit fixup corresponding to %b16(foo) for instructions like bne.
28 // 21-bit fixup corresponding to %b21(foo) for instructions like bnez.
30 // 26-bit fixup corresponding to %b26(foo)/%plt(foo) for instructions b/bl.
32 // 20-bit fixup corresponding to %abs_hi20(foo) for instruction lu12i.w.
34 // 12-bit fixup corresponding to %abs_lo12(foo) for instruction ori.
36 // 20-bit fixup corresponding to %abs64_lo20(foo) for instruction lu32i.d.
38 // 12-bit fixup corresponding to %abs_hi12(foo) for instruction lu52i.d.
40 // 20-bit fixup corresponding to %le_hi20(foo) for instruction lu12i.w.
42 // 12-bit fixup corresponding to %le_lo12(foo) for instruction ori.
44 // 20-bit fixup corresponding to %le64_lo20(foo) for instruction lu32i.d.
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Dreg.h9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_SOP_ASWRM BIT(31)
23 #define B_AX_SOP_PWMM_DSWR BIT(29)
24 #define B_AX_SOP_EDSWR BIT(28)
25 #define B_AX_XTAL_OFF_A_DIE BIT(22)
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H A Dtxrx.h71 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
72 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
73 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
76 #define RTW89_TXWD_BODY0_STF_MODE BIT(10)
77 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
78 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5)
90 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23)
95 #define RTW89_TXWD_BODY3_BK BIT(13)
96 #define RTW89_TXWD_BODY3_AGG_EN BIT(12)
112 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31)
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H A Dpci.h18 #define BAC_OOBS_SEL BIT(4)
20 #define B_BAC_EQ_SEL BIT(5)
24 #define B_PCIE_BIT_PSAVE BIT(15)
26 #define OFFSET_CAL_MODE BIT(13)
27 #define BAC_RX_TEST_EN BIT(6)
32 #define B_PCIE_BIT_PINOUT_DIS BIT(3)
34 #define BAC_CMU_EN_DLY_MASK GENMASK(15, 12)
37 #define B_PCIE_BIT_RD_SEL BIT(2)
45 #define OOBS_LEVEL_MASK GENMASK(12, 8)
54 #define B_AX_CLK_CALIB_EN BIT(12)
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H A Dfw.h26 #define RTW89_C2HREG_HDR_ACK BIT(7)
28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
107 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
421 #define RTW89_H2C_RA_W0_IS_DIS BIT(0)
425 #define RTW89_H2C_RA_W0_DCM BIT(16)
426 #define RTW89_H2C_RA_W0_ER BIT(17)
428 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
429 #define RTW89_H2C_RA_W0_SGI BIT(21)
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/freebsd/contrib/file/magic/Magdir/
H A Dmach9 # if set, it's for the 64-bit version of the architecture
10 # yes, this is separate from the low-order magic number bit
11 # it's also separate from the "64-bit libraries" bit in the
20 # 32-bit ABIs.
36 >>>4 belong&0x00ffffff 12 uvaxIII
37 >>>4 belong&0x00ffffff >12 vax subarchitecture=%d
84 >>>4 belong&0x0000000f 12 xeon
88 >>>4 belong&0x0000000f >12 ia32 family=%d
106 >>0 belong&0x00ffffff 12 arm
119 >>>4 belong&0x00ffffff 12 \bv7k
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H A Daudio12 >12 belong 1 8-bit ISDN mu-law,
14 >12 belong 2 8-bit linear PCM [REF-PCM],
16 >12 belong 3 16-bit linear PCM,
18 >12 belong 4 24-bit linear PCM,
20 >12 belong 5 32-bit linear PCM,
22 >12 belong 6 32-bit IEEE floating point,
24 >12 belong 7 64-bit IEEE floating point,
26 >12 belong 8 Fragmented sample data,
27 >12 belong 10 DSP program,
28 >12 belong 11 8-bit fixed point,
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/freebsd/sys/contrib/dev/rtw88/
H A Drtw8821c.c74 hal->pkg_type = map->rfe_option & BIT(5) ? 1 : 0; in rtw8821c_read_efuse()
191 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); in rtw8821c_phy_set_param()
228 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); in rtw8821c_mac_init()
258 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); in rtw8821c_mac_init()
272 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); in rtw8821c_cfg_ldo25()
348 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); in rtw8821c_set_channel_rf()
352 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); in rtw8821c_set_channel_rf()
357 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8821c_set_channel_rf()
358 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); in rtw8821c_set_channel_rf()
365 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
[all …]
H A Dtx.h27 #define RTW_TX_DESC_W0_BMC BIT(24)
28 #define RTW_TX_DESC_W0_LS BIT(26)
29 #define RTW_TX_DESC_W0_DISQSELSEQ BIT(31)
31 #define RTW_TX_DESC_W1_QSEL GENMASK(12, 8)
35 #define RTW_TX_DESC_W1_MORE_DATA BIT(29)
36 #define RTW_TX_DESC_W2_AGG_EN BIT(12)
37 #define RTW_TX_DESC_W2_SPE_RPT BIT(19)
39 #define RTW_TX_DESC_W2_BT_NULL BIT(23)
41 #define RTW_TX_DESC_W3_USE_RATE BIT(
[all...]
H A Drtw8822c.h164 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
182 #define BIT_LDOE25_PON BIT(0)
199 #define BITS_SUBTUNE GENMASK(15, 12)
210 #define BIT_PT_OPT BIT(21)
213 #define BIT_PATH_EN BIT(31)
215 #define BIT_DIS_SHARERX_TXGAT BIT(27)
216 #define BIT_3WIRE_TX_EN BIT(0)
217 #define BIT_3WIRE_RX_EN BIT(1)
219 #define BIT_3WIRE_PI_ON BIT(28)
221 #define BIT_ANAPAR_UPDATE BIT(2
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dmac.h10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
35 #define MT_RXD1_NORMAL_BEACON_MC BIT(4)
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H A Dregs.h28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
43 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVFixupKinds.h20 // 20-bit fixup corresponding to %hi(foo) for instructions like lui
22 // 12-bit fixup corresponding to %lo(foo) for instructions like addi
24 // 12-bit fixup corresponding to foo-bar for instructions like addi
26 // 12-bit fixup corresponding to %lo(foo) for the S-type store instructions
28 // 20-bit fixup corresponding to %pcrel_hi(foo) for instructions like auipc
30 // 12-bit fixu
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/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dtda1997x.txt6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
17 - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac2_mac.h42 #define MT_TX_FREE_COUNT GENMASK(12, 0)
46 #define MT_TX_FREE_PAIR BIT(31)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
58 #define MT_TXD1_AMSDU BIT(23)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
67 #define MT_TXD2_FIX_RATE BIT(31)
68 #define MT_TXD2_FIXED_RATE BIT(30)
72 #define MT_TXD2_HTC_VLD BIT(13)
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H A Dmt76_connac3_mac.h28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
38 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
39 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
40 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
41 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
42 #define MT_RXD1_NORMAL_GROUP_5 BIT(20)
44 #define MT_RXD1_NORMAL_CM BIT(23)
45 #define MT_RXD1_NORMAL_CLM BIT(24)
46 #define MT_RXD1_NORMAL_ICV_ERR BIT(25)
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/freebsd/sys/dev/sfxge/common/
H A Defx_regs.h48 * FR_AB_EE_VPD_CFG0_REG_SF(128bit):
54 * FR_AB_EE_VPD_CFG0_REG(128bit):
94 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit):
100 * FR_AB_PCIE_SD_CTL0123_REG(128bit):
162 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit):
168 * FR_AB_PCIE_SD_CTL45_REG(128bit):
198 #define FRF_AB_PCIE_DEQ3_LBN 12
208 * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit):
214 * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit):
234 #define FRF_AB_PCIE_CTCDISABLE_L_LBN 12
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H A Defx_regs_pci.h41 * PC_VEND_ID_REG(16bit):
52 * PC_DEV_ID_REG(16bit):
63 * PC_CMD_REG(16bit):
94 * PC_STAT_REG(16bit):
107 #define PCRF_AZ_GOT_TABRT_LBN 12
125 * PC_REV_ID_REG(8bit):
136 * PC_CC_REG(24bit):
151 * PC_CACHE_LSIZE_REG(8bit):
162 * PC_MST_LAT_REG(8bit):
173 * PC_HDR_TYPE_REG(8bit):
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmac.h15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
27 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
28 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
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/freebsd/sys/amd64/vmm/amd/
H A Damdvi_priv.h37 #define BIT(n) (1ULL << (n)) macro
38 /* Return value of bits[n:m] where n and (n >= ) m are bit positions. */
45 #define AMDVI_PCI_CAP_IOTLB BIT(0) /* IOTLB is supported. */
46 #define AMDVI_PCI_CAP_HT BIT(1) /* HyperTransport tunnel support. */
47 #define AMDVI_PCI_CAP_NPCACHE BIT(2) /* Not present page cached. */
48 #define AMDVI_PCI_CAP_EFR BIT(3) /* Extended features. */
49 #define AMDVI_PCI_CAP_EXT BIT(4) /* Miscellaneous information reg. */
54 #define AMDVI_EX_FEA_PREFSUP BIT(0) /* Prefetch command support. */
55 #define AMDVI_EX_FEA_PPRSUP BIT(1) /* PPR support */
56 #define AMDVI_EX_FEA_XTSUP BIT(2) /* Reserved */
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmc13xxx.txt55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
59 sw3 : regulator SW3 (register 29, bit 20)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
63 vdig : regulator VDIG (register 32, bit 9)
64 vgen : regulator VGEN (register 32, bit 12)
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMFixupKinds.h17 // 12-bit PC relative relocation for symbol addresses
20 // Equivalent to fixup_arm_ldst_pcrel_12, with the 16-bit halfwords reordered.
23 // 10-bit PC relative relocation for symbol addresses used in
26 // 10-bit PC relative relocation for symbol addresses used in VFP instructions
27 // where the lower 2 bits are not encoded (so it's encoded as an 8-bit
33 // 9-bit PC relative relocation for symbol addresses used in VFP instructions
34 // where bit 0 not encoded (so it's encoded as an 8-bit immediate).
39 // 12
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/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_reg.h20 * Register manipulation macros that expect bit field defines
28 #define BIT(_n) (1UL << (_n)) macro
51 #define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
101 #define AR40XX_MODULE_EN_MIB BIT(0)
104 #define AR40XX_MIB_BUSY BIT(17)
105 #define AR40XX_MIB_CPU_KEEP BIT(20)
112 #define AR40XX_ESS_SERVICE_TAG_STAG BIT(17)
136 #define AR40XX_PORT_TX_EN BIT(2)
137 #define AR40XX_PORT_RX_EN BIT(3)
138 #define AR40XX_PORT_STATUS_TXFLOW BIT(4)
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td64 class ExtMode<bit mode, string instSfx, string asmSfx> {
65 bit Value = mode;
76 class CacheMode<bit mode, string instSfx, string asmSfx> {
77 bit Value = mode;
129 // All 32-bit ARC instructions have a 5-bit "major" opcode class designator
133 // N - Delay Slot bit. ARC v2 branch instructions have an optional delay slot
134 // which is encoded with this bit. When set, a delay slot exists.
136 // SX - Signed X-bit immediate.
137 // UX - Unsigned X-bit immediate.
139 // [ABC] - 32-bit register operand. These are 6-bit fields. This encodes the
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/freebsd/sys/arm64/rockchip/
H A Drk_pinctrl.c77 uint32_t bit; member
131 .bit = _bit, \
209 RK_PINDRIVE(0, 0, 0x070, 3, 12),
215 RK_PINDRIVE(0, 1, 0x074, 3, 12),
221 RK_PINDRIVE(0, 2, 0x078, 3, 12),
227 RK_PINDRIVE(1, 3, 0x1CC, 3, 12),
233 RK_PINDRIVE(2, 0, 0x1D0, 3, 12),
239 RK_PINDRIVE(2, 1, 0x1D4, 3, 12),
245 RK_PINDRIVE(2, 2, 0x1D8, 3, 12),
251 RK_PINDRIVE(2, 3, 0x1DC, 3, 12),
[all …]

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