Lines Matching +full:12 +full:bit
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
31 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
32 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
40 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
41 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
42 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
43 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
44 #define MT_RXD1_NORMAL_GROUP_5 BIT(20)
46 #define MT_RXD1_NORMAL_CM BIT(23)
47 #define MT_RXD1_NORMAL_CLM BIT(24)
48 #define MT_RXD1_NORMAL_ICV_ERR BIT(25)
49 #define MT_RXD1_NORMAL_TKIP_MIC_ERR BIT(26)
51 #define MT_RXD1_NORMAL_SPP_EN BIT(29)
52 #define MT_RXD1_NORMAL_ADD_OM BIT(30)
53 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
57 #define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)
58 #define MT_RXD2_NORMAL_HDR_TRANS BIT(7)
61 #define MT_RXD2_NORMAL_MU_BAR BIT(21)
62 #define MT_RXD2_NORMAL_SW_BIT BIT(22)
63 #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
64 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
65 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)
66 #define MT_RXD2_NORMAL_INT_FRAME BIT(26)
67 #define MT_RXD2_NORMAL_FRAG BIT(27)
68 #define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
69 #define MT_RXD2_NORMAL_NDATA BIT(29)
70 #define MT_RXD2_NORMAL_NON_AMPDU BIT(30)
71 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
77 #define MT_RXD3_NORMAL_U2M BIT(0)
78 #define MT_RXD3_NORMAL_HTC_VLD BIT(18)
79 #define MT_RXD3_NORMAL_BEACON_MC BIT(20)
80 #define MT_RXD3_NORMAL_BEACON_UC BIT(21)
81 #define MT_RXD3_NORMAL_CO_ANT BIT(22)
82 #define MT_RXD3_NORMAL_FCS_ERR BIT(24)
83 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
88 #define MT_RXD4_MID_AMSDU_FRAME BIT(1)
89 #define MT_RXD4_LAST_AMSDU_FRAME BIT(0)
91 #define MT_RXV_HDR_BAND_IDX BIT(24)
103 #define MT_PRXV_TX_DCM BIT(4)
104 #define MT_PRXV_TX_ER_SU_106T BIT(5)
106 #define MT_PRXV_TXBF BIT(11)
107 #define MT_PRXV_HT_AD_CODE BIT(12)
117 #define MT_PRXV_DCM BIT(5)
122 #define MT_CRXV_HE_LDPC_EXT_SYM BIT(30)
124 #define MT_CRXV_HE_PE_DISAMBIG BIT(1)
125 #define MT_CRXV_HE_UPLINK BIT(2)
128 #define MT_CRXV_HE_BEAM_CHNG BIT(29)
130 #define MT_CRXV_HE_DOPPLER BIT(0)
135 #define MT_CRXV_HE_SR1_MASK GENMASK(16, 12)
178 #define MT_CT_INFO_APPLY_TXD BIT(0)
179 #define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
180 #define MT_CT_INFO_MGMT_FRAME BIT(2)
181 #define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
182 #define MT_CT_INFO_HSR2_TX BIT(4)
183 #define MT_CT_INFO_FROM_HOST BIT(7)
192 #define MT_TXD1_FIXED_RATE BIT(31)
195 #define MT_TXD1_BIP BIT(24)
196 #define MT_TXD1_ETH_802_3 BIT(20)
199 #define MT_TXD1_TGID GENMASK(13, 12)
205 #define MT_TXD2_HTC_VLD BIT(13)
206 #define MT_TXD2_DURATION BIT(12)
208 #define MT_TXD2_RTS BIT(9)
209 #define MT_TXD2_OWN_MAC_MAP BIT(8)
214 #define MT_TXD3_SN_VALID BIT(31)
215 #define MT_TXD3_PN_VALID BIT(30)
216 #define MT_TXD3_SW_POWER_MGMT BIT(29)
217 #define MT_TXD3_BA_DISABLE BIT(28)
221 #define MT_TXD3_HW_AMSDU BIT(5)
222 #define MT_TXD3_BCM BIT(4)
223 #define MT_TXD3_EEOSP BIT(3)
224 #define MT_TXD3_EMRD BIT(2)
225 #define MT_TXD3_PROTECT_FRAME BIT(1)
226 #define MT_TXD3_NO_ACK BIT(0)
231 #define MT_TXD5_FL BIT(15)
232 #define MT_TXD5_BYPASS_TBB BIT(14)
233 #define MT_TXD5_BYPASS_RBB BIT(13)
234 #define MT_TXD5_BSS_COLOR_ZERO BIT(12)
235 #define MT_TXD5_TX_STATUS_HOST BIT(10)
236 #define MT_TXD5_TX_STATUS_MCU BIT(9)
237 #define MT_TXD5_TX_STATUS_FMT BIT(8)
241 #define MT_TXD6_VTA BIT(28)
244 #define MT_TXD6_TIMESTAMP_OFS_EN BIT(15)
247 #define MT_TXD6_DIS_MAT BIT(3)
248 #define MT_TXD6_DAS BIT(2)
249 #define MT_TXD6_AMSDU_CAP BIT(1)
252 #define MT_TXD7_IP_SUM BIT(29)
253 #define MT_TXD7_DROP_BY_SDO BIT(28)
254 #define MT_TXD7_MAC_TXD BIT(27)
255 #define MT_TXD7_CTXD BIT(26)
257 #define MT_TXD7_UDP_TCP_SUM BIT(15)
260 #define MT_TX_RATE_STBC BIT(14)
263 #define MT_TX_RATE_SU_EXT_TONE BIT(5)
264 #define MT_TX_RATE_DCM BIT(4)
274 #define MT_TXFREE_INFO_PAIR BIT(31)
275 #define MT_TXFREE_INFO_HEADER BIT(30)
276 #define MT_TXFREE_INFO_WLAN_ID GENMASK(23, 12)
283 #define MT_TXS0_AMPDU BIT(25)
285 #define MT_TXS0_BA_ERROR BIT(22)
286 #define MT_TXS0_PS_FLAG BIT(21)
287 #define MT_TXS0_TXOP_TIMEOUT BIT(20)
288 #define MT_TXS0_BIP_ERROR BIT(19)
290 #define MT_TXS0_QUEUE_TIMEOUT BIT(18)
291 #define MT_TXS0_RTS_TIMEOUT BIT(17)
292 #define MT_TXS0_ACK_TIMEOUT BIT(16)
295 #define MT_TXS0_TX_STATUS_HOST BIT(15)
296 #define MT_TXS0_TX_STATUS_MCU BIT(14)
310 #define MT_TXS3_RATE_STBC BIT(7)
311 #define MT_TXS3_FIXED_RATE BIT(6)
313 #define MT_TXS3_SHARED_ANTENNA BIT(3)
318 #define MT_TXS5_F0_FINAL_MPDU BIT(31)
319 #define MT_TXS5_F0_QOS BIT(30)