Lines Matching +full:12 +full:bit
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
91 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
389 #define RTW89_H2C_RA_W0_IS_DIS BIT(0)
393 #define RTW89_H2C_RA_W0_DCM BIT(16)
394 #define RTW89_H2C_RA_W0_ER BIT(17)
396 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
397 #define RTW89_H2C_RA_W0_SGI BIT(21)
398 #define RTW89_H2C_RA_W0_LDPC BIT(22)
399 #define RTW89_H2C_RA_W0_STBC BIT(23)
402 #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
403 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
406 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
408 #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
409 #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
410 #define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
411 #define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
412 #define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12)
451 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
456 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
486 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
491 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
504 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
534 #define FWSECTION_HDR_W1_CHECKSUM BIT(28)
535 #define FWSECTION_HDR_W1_REDL BIT(29)
565 #define FW_HDR_W7_DYN_HDR BIT(16)
579 #define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
580 #define FWSECTION_HDR_V1_W1_REDL BIT(29)
615 #define FW_HDR_V1_W6_DSP_CHKSUM BIT(24)
617 #define FW_HDR_V1_W7_DYN_HDR BIT(16)
659 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
668 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
671 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
673 BIT(9));
685 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
687 GENMASK(14, 12));
689 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
692 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
694 BIT(15));
703 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
706 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
708 BIT(20));
710 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
713 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
715 BIT(21));
717 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
720 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
722 BIT(22));
724 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
727 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
729 BIT(23));
731 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
734 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
736 BIT(25));
738 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
741 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
743 BIT(26));
745 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
748 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
750 BIT(27));
766 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
769 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
771 BIT(9));
773 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
776 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
778 BIT(10));
780 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
783 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
785 BIT(11));
790 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
792 GENMASK(15, 12));
801 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
804 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
806 BIT(27));
822 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
825 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
827 BIT(6));
829 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
832 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
834 BIT(7));
836 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
839 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
841 BIT(8));
843 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
846 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
848 BIT(9));
857 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
860 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
862 BIT(12));
878 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
881 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
883 BIT(27));
896 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
903 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
910 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
917 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
924 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
931 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
938 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
948 #define SET_CMC_TBL_MASK_BMC BIT(0)
951 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
953 BIT(3));
962 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
965 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
967 BIT(8));
976 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
979 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
981 BIT(12));
983 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
986 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
988 BIT(13));
990 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
993 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
995 BIT(14));
997 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
1000 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1002 BIT(15));
1004 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
1007 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
1009 BIT(16));
1011 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
1014 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
1016 BIT(17));
1018 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
1021 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
1023 BIT(18));
1025 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
1028 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
1030 BIT(19));
1032 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
1035 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
1037 BIT(20));
1039 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
1042 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
1044 BIT(21));
1046 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
1049 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
1051 BIT(27));
1067 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
1070 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
1072 BIT(12));
1074 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
1077 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
1079 BIT(13));
1116 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
1119 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
1121 BIT(28));
1123 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
1126 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1128 BIT(29));
1130 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
1133 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1135 BIT(30));
1137 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
1140 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1142 BIT(31));
1188 #define SET_CMC_TBL_MASK_ULDL BIT(0)
1191 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1193 BIT(17));
1264 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
1267 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1269 BIT(12));
1271 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
1274 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1276 BIT(13));
1278 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
1281 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1283 BIT(14));
1285 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
1288 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1290 BIT(15));
1359 #define CCTLINFO_G7_C0_OP BIT(7)
1362 #define CCTLINFO_G7_W0_DATA_GI_LTF GENMASK(14, 12)
1363 #define CCTLINFO_G7_W0_TRYRATE BIT(15)
1365 #define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18)
1366 #define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20)
1367 #define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21)
1368 #define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22)
1369 #define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23)
1370 #define CCTLINFO_G7_W0_FORCE_TXOP BIT(24)
1371 #define CCTLINFO_G7_W0_DISRTSFB BIT(25)
1372 #define CCTLINFO_G7_W0_DISDATAFB BIT(26)
1373 #define CCTLINFO_G7_W0_NSTR_EN BIT(27)
1377 #define CCTLINFO_G7_W1_RTS_TXCNT_LMT GENMASK(15, 12)
1382 #define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6)
1383 #define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)
1384 #define CCTLINFO_G7_W2_RTS_EN BIT(8)
1385 #define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9)
1387 #define CCTLINFO_G7_W2_HW_RTS_EN BIT(12)
1389 #define CCTLINFO_G7_W2_PRELD_EN BIT(15)
1391 #define CCTLINFO_G7_W2_UL_MU_DIS BIT(27)
1396 #define CCTLINFO_G7_W3_DATA_BW_ER BIT(11)
1397 #define CCTLINFO_G7_W3_BA_BMAP GENMASK(14, 12)
1398 #define CCTLINFO_G7_W3_VCS_STBC BIT(15)
1403 #define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28)
1404 #define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29)
1405 #define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30)
1406 #define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)
1409 #define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3)
1411 #define CCTLINFO_G7_W4_DATA_DCM BIT(8)
1412 #define CCTLINFO_G7_W4_DATA_ER BIT(9)
1413 #define CCTLINFO_G7_W4_DATA_LDPC BIT(10)
1414 #define CCTLINFO_G7_W4_DATA_STBC BIT(11)
1415 #define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12)
1416 #define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14)
1417 #define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15)
1419 #define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0))
1430 #define CCTLINFO_G7_W6_RESP_REF_RATE GENMASK(23, 12)
1431 #define CCTLINFO_G7_W6_ULDL BIT(31)
1432 #define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))
1438 #define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13)
1439 #define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14)
1440 #define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15)
1444 #define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0)
1445 #define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1)
1446 #define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2)
1447 #define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3)
1448 #define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4)
1449 #define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5)
1450 #define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6)
1451 #define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)
1453 #define CCTLINFO_G7_W8_RESP_SEC_TYPE GENMASK(15, 12)
1457 #define CCTLINFO_G7_W14_VI_CURR_RATE GENMASK(23, 12)
1478 #define RTW89_H2C_BCN_UPD_W1_RATE GENMASK(20, 12)
1480 #define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0)
1485 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D GENMASK(12, 11)
1486 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13)
1487 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14)
1488 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15)
1489 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16)
1532 #define RTW89_H2C_BCN_UPD_BE_W1_RATE GENMASK(20, 12)
1535 #define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0)
1540 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D GENMASK(12, 11)
1541 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13)
1542 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14)
1543 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15)
1544 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16)
1556 #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)
1570 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10));
1595 #define RTW89_H2C_JOININFO_W0_OP BIT(8)
1596 #define RTW89_H2C_JOININFO_W0_BAND BIT(9)
1598 #define RTW89_H2C_JOININFO_W0_TGR BIT(12)
1599 #define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13)
1608 #define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3)
1610 #define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12)
1611 #define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13)
1612 #define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14)
1613 #define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15)
1623 #define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)
1680 #define RTW89_H2C_BA_CAM_W0_VALID BIT(0)
1681 #define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1)
1688 #define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8)
1689 #define RTW89_H2C_BA_CAM_W1_BAND BIT(9)
1697 #define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0)
1698 #define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1)
1704 #define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8)
1705 #define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9)
1706 #define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10)
1714 #define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK GENMASK(19, 12)
1715 #define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24)
1744 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1749 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1754 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1759 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1855 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1860 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1865 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1893 #define RTW89_H2C_WOW_GLOBAL_W0_ENABLE BIT(0)
1894 #define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT BIT(1)
1895 #define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE BIT(2)
1896 #define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED BIT(3)
1903 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1908 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1913 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1918 le32p_replace_bits((__le32 *)h2c, val, BIT(3));
1923 le32p_replace_bits((__le32 *)h2c, val, BIT(4));
1928 le32p_replace_bits((__le32 *)h2c, val, BIT(5));
1933 le32p_replace_bits((__le32 *)h2c, val, BIT(6));
1938 le32p_replace_bits((__le32 *)h2c, val, BIT(7));
1948 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1983 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
1988 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
1993 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
1998 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
2003 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
2008 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
2017 #define RTW89_H2C_WOW_GTK_OFLD_W0_EN BIT(0)
2018 #define RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN BIT(1)
2019 #define RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN BIT(2)
2020 #define RTW89_H2C_WOW_GTK_OFLD_W0_PAIRWISE_WAKEUP BIT(3)
2021 #define RTW89_H2C_WOW_GTK_OFLD_W0_NOREKEY_WAKEUP BIT(4)
2033 #define RTW89_H2C_ARP_OFFLOAD_W0_ENABLE BIT(0)
2034 #define RTW89_H2C_ARP_OFFLOAD_W0_ACTION BIT(1)
2169 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2170 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2174 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2175 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2176 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2179 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2180 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2181 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2182 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2183 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2202 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2207 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2212 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2217 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2222 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2227 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2232 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2237 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2242 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2247 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2252 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2257 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2262 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2267 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2272 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2277 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2282 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2287 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2292 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2297 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2302 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2307 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2312 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2317 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2322 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2327 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2332 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2337 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2342 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2347 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2352 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2357 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2362 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2367 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2372 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2377 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2392 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2397 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2407 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2412 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2417 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2422 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2482 u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0));
2572 #define RTW89_H2C_CHINFO_W1_TX BIT(12)
2573 #define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13)
2576 #define RTW89_H2C_CHINFO_W1_DFS BIT(24)
2577 #define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25)
2578 #define RTW89_H2C_CHINFO_W1_RANDOM BIT(26)
2579 #define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27)
2606 #define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5)
2607 #define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6)
2608 #define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7)
2609 #define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8)
2611 #define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14)
2638 #define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0)
2639 #define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1)
2654 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2657 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2658 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2659 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2688 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23)
2692 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_BW GENMASK(12, 10)
2720 #define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6)
2721 #define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7)
2725 #define RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE BIT(29)
2758 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
2768 le32p_replace_bits((__le32 *)cmd, val, BIT(20));
2773 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2808 le32p_replace_bits((__le32 *)cmd, val, BIT(0));
2813 le32p_replace_bits((__le32 *)cmd, val, BIT(1));
2894 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
2899 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
2904 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
2919 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
2924 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
2929 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
2944 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
2984 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3004 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3034 le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3044 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3137 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3217 /* for MLD, bit X maps to macid: X + chip::support_mld_num */
3241 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24)
3242 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25)
3243 #define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26)
3244 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27)
3249 #define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22)
3250 #define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23)
3263 #define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17)
3280 #define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16)
3309 #define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4)
3310 #define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5)
3311 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6)
3351 #define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4)
3368 #define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0)
3370 #define RTW89_H2C_MRC_SYNC_W0_SRC_BAND GENMASK(15, 12)
3395 #define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16)
3469 #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3493 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3496 #define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
3498 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3499 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3540 #define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26)
3661 #define RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX BIT(0)
3667 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3668 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3669 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3672 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
3740 RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ = 12,
3753 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \
3754 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \
3755 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \
3756 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \
3757 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \
3758 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \
3759 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ) | \
3760 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \
3761 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU))
3763 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
3764 BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3765 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3766 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3767 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3768 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3800 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N = 12,
3814 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \
3815 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \
3816 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \
3817 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P))
3819 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \
3820 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \
3821 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \
3822 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P))
3824 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \
3825 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \
3826 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \
3827 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \
3828 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \
3829 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \
3830 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \
3831 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P))
3920 #define H2C_HDR_REC_ACK BIT(14)
3921 #define H2C_HDR_DONE_ACK BIT(15)
4024 /* CLASS 12 - BA CAM */