Lines Matching +full:12 +full:bit
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
35 #define MT_RXD1_NORMAL_BEACON_MC BIT(4)
36 #define MT_RXD1_NORMAL_BCAST BIT(3)
37 #define MT_RXD1_NORMAL_MCAST BIT(2)
38 #define MT_RXD1_NORMAL_U2M BIT(1)
39 #define MT_RXD1_NORMAL_HTC_VLD BIT(0)
41 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
42 #define MT_RXD2_NORMAL_NON_AMPDU_SUB BIT(30)
43 #define MT_RXD2_NORMAL_NDATA BIT(29)
44 #define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
45 #define MT_RXD2_NORMAL_FRAG BIT(27)
46 #define MT_RXD2_NORMAL_UDF_VALID BIT(26)
47 #define MT_RXD2_NORMAL_LLC_MIS BIT(25)
48 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
49 #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
50 #define MT_RXD2_NORMAL_LEN_MISMATCH BIT(22)
51 #define MT_RXD2_NORMAL_TKIP_MIC_ERR BIT(21)
52 #define MT_RXD2_NORMAL_ICV_ERR BIT(20)
53 #define MT_RXD2_NORMAL_CLM BIT(19)
54 #define MT_RXD2_NORMAL_CM BIT(18)
55 #define MT_RXD2_NORMAL_FCS_ERR BIT(17)
56 #define MT_RXD2_NORMAL_SW_BIT BIT(16)
57 #define MT_RXD2_NORMAL_SEC_MODE GENMASK(15, 12)
62 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
65 #define MT_RXD3_NORMAL_MAGIC_PKT BIT(13)
66 #define MT_RXD3_NORMAL_OFLD GENMASK(12, 11)
67 #define MT_RXD3_NORMAL_CLS BIT(10)
68 #define MT_RXD3_NORMAL_PATTERN_DROP BIT(9)
69 #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(8)
74 #define MT_RXV1_HT_NO_SOUND BIT(21)
75 #define MT_RXV1_HT_SMOOTH BIT(20)
76 #define MT_RXV1_HT_SHORT_GI BIT(19)
77 #define MT_RXV1_HT_AGGR BIT(18)
78 #define MT_RXV1_VHTA1_B22 BIT(17)
80 #define MT_RXV1_TX_MODE GENMASK(14, 12)
82 #define MT_RXV1_HT_AD_CODE BIT(9)
90 #define MT_RXV3_F_AGC1_EQ_CAL BIT(28)
93 #define MT_RXV3_F_AGC0_EQ_CAL BIT(16)
95 #define MT_RXV3_SEL_ANT BIT(7)
96 #define MT_RXV3_ACI_DET_X BIT(6)
97 #define MT_RXV3_OFDM_FREQ_TRANS_DETECT BIT(5)
101 #define MT_RXV4_F_AGC2_EQ_CAL BIT(28)
116 #define MT_RXV6_RX_VALID BIT(24)
130 #define MT_TXD0_P_IDX BIT(31)
132 #define MT_TXD0_UTXB BIT(26)
133 #define MT_TXD0_UNXV BIT(25)
134 #define MT_TXD0_UDP_TCP_SUM BIT(24)
135 #define MT_TXD0_IP_SUM BIT(23)
140 #define MT_TXD1_PROTECTED BIT(23)
142 #define MT_TXD1_NO_ACK BIT(19)
144 #define MT_TXD1_LONG_FORMAT BIT(15)
146 #define MT_TXD1_HDR_INFO GENMASK(12, 8)
149 #define MT_TXD2_FIX_RATE BIT(31)
150 #define MT_TXD2_TIMING_MEASURE BIT(30)
151 #define MT_TXD2_BA_DISABLE BIT(29)
155 #define MT_TXD2_HTC_VLD BIT(13)
156 #define MT_TXD2_DURATION BIT(12)
157 #define MT_TXD2_BIP BIT(11)
158 #define MT_TXD2_MULTICAST BIT(10)
159 #define MT_TXD2_RTS BIT(9)
160 #define MT_TXD2_SOUNDING BIT(8)
161 #define MT_TXD2_NDPA BIT(7)
162 #define MT_TXD2_NDP BIT(6)
166 #define MT_TXD3_SN_VALID BIT(31)
167 #define MT_TXD3_PN_VALID BIT(30)
175 #define MT_TXD5_SW_POWER_MGMT BIT(13)
176 #define MT_TXD5_BA_SEQ_CTRL BIT(12)
177 #define MT_TXD5_DA_SELECT BIT(11)
178 #define MT_TXD5_TX_STATUS_HOST BIT(10)
179 #define MT_TXD5_TX_STATUS_MCU BIT(9)
180 #define MT_TXD5_TX_STATUS_FMT BIT(8)
183 #define MT_TXD6_SGI BIT(31)
184 #define MT_TXD6_LDPC BIT(30)
186 #define MT_TXD6_I_TXBF BIT(17)
187 #define MT_TXD6_E_TXBF BIT(16)
188 #define MT_TXD6_DYN_BW BIT(15)
189 #define MT_TXD6_ANT_PRI GENMASK(14, 12)
190 #define MT_TXD6_SPE_EN BIT(11)
191 #define MT_TXD6_FIXED_BW BIT(10)
194 #define MT_TXD6_FIXED_RATE BIT(0)
196 #define MT_TX_RATE_STBC BIT(11)
203 #define MT_TXS0_BA_ERROR BIT(22)
204 #define MT_TXS0_PS_FLAG BIT(21)
205 #define MT_TXS0_TXOP_TIMEOUT BIT(20)
206 #define MT_TXS0_BIP_ERROR BIT(19)
208 #define MT_TXS0_QUEUE_TIMEOUT BIT(18)
209 #define MT_TXS0_RTS_TIMEOUT BIT(17)
210 #define MT_TXS0_ACK_TIMEOUT BIT(16)
213 #define MT_TXS0_TX_STATUS_HOST BIT(15)
214 #define MT_TXS0_TX_STATUS_MCU BIT(14)
215 #define MT_TXS0_TXS_FORMAT BIT(13)
216 #define MT_TXS0_FIXED_RATE BIT(12)
235 #define MT_TXS4_AMPDU BIT(23)
236 #define MT_TXS4_ACKED_MPDU BIT(22)
238 #define MT_TXS4_BW GENMASK(13, 12)