Lines Matching +full:12 +full:bit
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
43 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
45 #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6)
46 #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
48 #define MT_WPDMA_GLO_CFG_SW_RESET BIT(24)
49 #define MT_WPDMA_GLO_CFG_FORCE_TX_EOF BIT(25)
50 #define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30)
51 #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
57 #define MT_WPDMA_DEBUG_SEL BIT(27)
75 #define MT_SCH_4_BYPASS BIT(5)
76 #define MT_SCH_4_RESET BIT(8)
99 #define MT_MCU_DEBUG_RESET_PSE BIT(0)
100 #define MT_MCU_DEBUG_RESET_PSE_S BIT(1)
112 #define MT_PSE_FRP_P2_RQ2 GENMASK(14, 12)
127 #define MT_PSE_RTA_REDIRECT_EN BIT(7)
129 #define MT_PSE_RTA_WRITE BIT(16)
130 #define MT_PSE_RTA_BUSY BIT(31)
153 #define MT_RXTD_13_ACI_TH_EN BIT(0)
163 #define MT_PHYCTRL_2_STATUS_RESET BIT(6)
164 #define MT_PHYCTRL_2_STATUS_EN BIT(7)
178 #define MT_AGG_ARCR_INIT_RATE1 BIT(0)
179 #define MT_AGG_ARCR_FB_SGI_DISABLE BIT(1)
180 #define MT_AGG_ARCR_RATE8_DOWN_WRAP BIT(2)
181 #define MT_AGG_ARCR_RTS_RATE_THR GENMASK(12, 8)
183 #define MT_AGG_ARCR_RATE_DOWN_RATIO_EN BIT(19)
203 #define MT_AGG_PCR_MM BIT(16)
204 #define MT_AGG_PCR_GF BIT(17)
205 #define MT_AGG_PCR_BW40 BIT(18)
206 #define MT_AGG_PCR_RIFS BIT(19)
207 #define MT_AGG_PCR_BW80 BIT(20)
208 #define MT_AGG_PCR_BW160 BIT(21)
209 #define MT_AGG_PCR_ERP BIT(22)
219 #define MT_AGG_CONTROL_NO_BA_RULE BIT(0)
220 #define MT_AGG_CONTROL_NO_BA_AR_RULE BIT(1)
221 #define MT_AGG_CONTROL_CFEND_SPE_EN BIT(3)
223 #define MT_AGG_CONTROL_BAR_SPE_EN BIT(19)
233 #define MT_AGG_RETRY_CONTROL_BAR_LIMIT GENMASK(15, 12)
240 #define MT_DMA_DCR0_DAMSDU BIT(16)
241 #define MT_DMA_DCR0_RX_VEC_DROP BIT(17)
251 #define MT_DMA_FQCR0_MODE BIT(29)
252 #define MT_DMA_FQCR0_STATUS BIT(30)
253 #define MT_DMA_FQCR0_BUSY BIT(31)
261 #define MT_DMA_TCFR_TXS_QUEUE BIT(14)
262 #define MT_DMA_TCFR_TXS_AGGR_COUNT GENMASK(12, 8)
284 #define MT_WF_ARB_RQCR_RX_START BIT(0)
285 #define MT_WF_ARB_RQCR_RXV_START BIT(4)
286 #define MT_WF_ARB_RQCR_RXV_R_EN BIT(7)
287 #define MT_WF_ARB_RQCR_RXV_T_EN BIT(8)
292 #define MT_ARB_SCR_TX_DISABLE BIT(8)
293 #define MT_ARB_SCR_RX_DISABLE BIT(9)
294 #define MT_ARB_SCR_BCNQ_EMPTY_SKIP BIT(28)
295 #define MT_ARB_SCR_TTTT_BTIM_PRIO BIT(29)
296 #define MT_ARB_SCR_TBTT_BCN_PRIO BIT(30)
297 #define MT_ARB_SCR_TBTT_BCAST_PRIO BIT(31)
312 #define MT_WF_ARB_TX_FLUSH_AC0 BIT(0)
313 #define MT_WF_ARB_TX_FLUSH_AC1 BIT(5)
314 #define MT_WF_ARB_TX_FLUSH_AC2 BIT(10)
315 #define MT_WF_ARB_TX_FLUSH_AC3 BIT(16)
316 #define MT_WF_ARB_TX_FLUSH_AC4 BIT(21)
317 #define MT_WF_ARB_TX_FLUSH_AC5 BIT(26)
320 #define MT_WF_ARB_BCN_START_BSSn(n) BIT(0 + (n))
321 #define MT_WF_ARB_BCN_START_T_PRE_TTTT BIT(10)
322 #define MT_WF_ARB_BCN_START_T_TTTT BIT(11)
323 #define MT_WF_ARB_BCN_START_T_PRE_TBTT BIT(12)
324 #define MT_WF_ARB_BCN_START_T_TBTT BIT(13)
325 #define MT_WF_ARB_BCN_START_T_SLOT_IDLE BIT(14)
326 #define MT_WF_ARB_BCN_START_T_TX_START BIT(15)
327 #define MT_WF_ARB_BCN_START_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)
330 #define MT_WF_ARB_BCN_FLUSH_BSSn(n) BIT(0 + (n))
331 #define MT_WF_ARB_BCN_FLUSH_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)
334 #define MT_WF_ARB_CAB_START_BSSn(n) BIT(0 + (n))
335 #define MT_WF_ARB_CAB_START_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)
338 #define MT_WF_ARB_CAB_FLUSH_BSSn(n) BIT(0 + (n))
339 #define MT_WF_ARB_CAB_FLUSH_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)
344 #define MT_WF_ARB_CAB_COUNT_B0_REG(n) MT_WF_ARB_CAB_COUNT(((n) > 12 ? 2 : \
346 #define MT_WF_ARB_CAB_COUNT_B0_SHIFT(n) (((n) > 12 ? (n) - 12 : \
351 #define MT_TX_ABORT_EN BIT(0)
360 #define MT_TMAC_TCR_PRE_RTS_SEC_IDLE GENMASK(13, 12)
361 #define MT_TMAC_TCR_RTS_SIGTA BIT(14)
362 #define MT_TMAC_TCR_LDPC_OFS BIT(15)
365 #define MT_TMAC_TCR_SCH_DET_PER_IOD BIT(20)
366 #define MT_TMAC_TCR_DCH_DET_DISABLE BIT(21)
367 #define MT_TMAC_TCR_TX_RIFS BIT(22)
368 #define MT_TMAC_TCR_RX_RIFS_MODE BIT(23)
369 #define MT_TMAC_TCR_TXOP_TBTT_CTL BIT(24)
370 #define MT_TMAC_TCR_TBTT_TX_STOP_CTL BIT(25)
371 #define MT_TMAC_TCR_TXOP_BURST_STOP BIT(26)
372 #define MT_TMAC_TCR_RDG_RA_MODE BIT(27)
373 #define MT_TMAC_TCR_RDG_RESP BIT(29)
374 #define MT_TMAC_TCR_RDG_NO_PENDING BIT(30)
375 #define MT_TMAC_TCR_SMOOTHING BIT(31)
402 #define MT_TMAC_PCR_RATE_FIXED BIT(15)
404 #define MT_TMAC_PCR_ANT_ID_SEL BIT(22)
405 #define MT_TMAC_PCR_SPE_EN BIT(23)
413 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
414 #define MT_WF_RFCR_DROP_FCSFAIL BIT(1)
415 #define MT_WF_RFCR_DROP_VERSION BIT(3)
416 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4)
417 #define MT_WF_RFCR_DROP_MCAST BIT(5)
418 #define MT_WF_RFCR_DROP_BCAST BIT(6)
419 #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7)
420 #define MT_WF_RFCR_DROP_A3_MAC BIT(8)
421 #define MT_WF_RFCR_DROP_A3_BSSID BIT(9)
422 #define MT_WF_RFCR_DROP_A2_BSSID BIT(10)
423 #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11)
424 #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12)
425 #define MT_WF_RFCR_DROP_CTL_RSV BIT(13)
426 #define MT_WF_RFCR_DROP_CTS BIT(14)
427 #define MT_WF_RFCR_DROP_RTS BIT(15)
428 #define MT_WF_RFCR_DROP_DUPLICATE BIT(16)
429 #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17)
430 #define MT_WF_RFCR_DROP_OTHER_UC BIT(18)
431 #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19)
432 #define MT_WF_RFCR_DROP_NDPA BIT(20)
433 #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)
437 #define MT_BSSID1_VALID BIT(16)
442 #define MT_MAC_ADDR1_VALID BIT(16)
448 #define MT_BA_CONTROL_1_IGNORE_TID BIT(20)
449 #define MT_BA_CONTROL_1_IGNORE_ALL BIT(21)
450 #define MT_BA_CONTROL_1_RESET BIT(22)
453 #define MT_WF_RMACDR_TSF_PROBERSP_DIS BIT(0)
454 #define MT_WF_RMACDR_TSF_TIM BIT(4)
456 #define MT_WF_RMACDR_CHECK_HTC_BY_RATE BIT(26)
457 #define MT_WF_RMACDR_MAXLEN_20BIT BIT(30)
462 #define MT_WF_RMAC_RMCR_SMPS_RTS BIT(25)
480 #define MT_WTBL_UPDATE_WTBL2 BIT(11)
481 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12)
482 #define MT_WTBL_UPDATE_RATE_UPDATE BIT(13)
483 #define MT_WTBL_UPDATE_TX_COUNT_CLEAR BIT(14)
484 #define MT_WTBL_UPDATE_RX_COUNT_CLEAR BIT(15)
485 #define MT_WTBL_UPDATE_BUSY BIT(16)
488 #define MT_WTBL_RMVTCR_RX_MV_MODE BIT(23)
511 #define MT_TBTT_CAL_ENABLE BIT(31)
516 #define MT_LPON_SBTOR_SUB_BSS_EN BIT(29)
525 #define MT_HW_INT3_TBTT0 BIT(15)
526 #define MT_HW_INT3_PRE_TBTT0 BIT(31)
537 #define MT_WTBL_RIUCR1_RATE1 GENMASK(23, 12)
558 #define MT_MIB_CTL_READ_CLR_DIS BIT(31)
586 #define MT_LED_CTRL_REPLAY(_n) BIT(0 + (8 * (_n)))
587 #define MT_LED_CTRL_POLARITY(_n) BIT(1 + (8 * (_n)))
588 #define MT_LED_CTRL_TX_BLINK_MODE(_n) BIT(2 + (8 * (_n)))
589 #define MT_LED_CTRL_TX_MANUAL_BLINK(_n) BIT(3 + (8 * (_n)))
590 #define MT_LED_CTRL_TX_OVER_BLINK(_n) BIT(5 + (8 * (_n)))
591 #define MT_LED_CTRL_KICK(_n) BIT(7 + (8 * (_n)))
606 #define MT_CLIENT_RESET_TX_R_E_1 BIT(16)
607 #define MT_CLIENT_RESET_TX_R_E_2 BIT(17)
608 #define MT_CLIENT_RESET_TX_R_E_1_S BIT(20)
609 #define MT_CLIENT_RESET_TX_R_E_2_S BIT(21)
614 #define MT_EFUSE_BASE_CTRL_EMPTY BIT(30)
622 #define MT_EFUSE_CTRL_VALID BIT(29)
623 #define MT_EFUSE_CTRL_KICK BIT(30)
624 #define MT_EFUSE_CTRL_SEL BIT(31)
646 #define MT_WTBL1_W0_RX_CHECK_A1 BIT(22)
648 #define MT_WTBL1_W0_RX_CHECK_KEY_IDX BIT(25)
649 #define MT_WTBL1_W0_RX_KEY_VALID BIT(26)
650 #define MT_WTBL1_W0_RX_IK_VALID BIT(27)
651 #define MT_WTBL1_W0_RX_VALID BIT(28)
652 #define MT_WTBL1_W0_RX_CHECK_A2 BIT(29)
653 #define MT_WTBL1_W0_RX_DATA_VALID BIT(30)
654 #define MT_WTBL1_W0_WRITE_BURST BIT(31)
660 #define MT_WTBL1_W2_EVEN_PN BIT(7)
661 #define MT_WTBL1_W2_TO_DS BIT(8)
662 #define MT_WTBL1_W2_FROM_DS BIT(9)
663 #define MT_WTBL1_W2_HEADER_TRANS BIT(10)
665 #define MT_WTBL1_W2_PWR_MGMT BIT(14)
666 #define MT_WTBL1_W2_RDG BIT(15)
667 #define MT_WTBL1_W2_RTS BIT(16)
668 #define MT_WTBL1_W2_CFACK BIT(17)
669 #define MT_WTBL1_W2_RDG_BA BIT(18)
670 #define MT_WTBL1_W2_SMPS BIT(19)
671 #define MT_WTBL1_W2_TXS_BAF_REPORT BIT(20)
672 #define MT_WTBL1_W2_DYN_BW BIT(21)
673 #define MT_WTBL1_W2_LDPC BIT(22)
674 #define MT_WTBL1_W2_ITXBF BIT(23)
675 #define MT_WTBL1_W2_ETXBF BIT(24)
676 #define MT_WTBL1_W2_TXOP_PS BIT(25)
677 #define MT_WTBL1_W2_MESH BIT(26)
678 #define MT_WTBL1_W2_QOS BIT(27)
679 #define MT_WTBL1_W2_HT BIT(28)
680 #define MT_WTBL1_W2_VHT BIT(29)
681 #define MT_WTBL1_W2_ADMISSION_CONTROL BIT(30)
682 #define MT_WTBL1_W2_GROUP_ID BIT(31)
687 #define MT_WTBL1_W3_CHECK_PER BIT(27)
688 #define MT_WTBL1_W3_KEEP_I_PSM BIT(28)
689 #define MT_WTBL1_W3_I_PSM BIT(29)
690 #define MT_WTBL1_W3_POWER_SAVE BIT(30)
691 #define MT_WTBL1_W3_SKIP_TX BIT(31)
704 #define MT_WTBL2_W2_TID1_SN GENMASK(23, 12)
731 #define MT_WTBL2_W9_SPATIAL_EXT BIT(5)
736 #define MT_WTBL2_W9_SHORT_GI_20 BIT(16)
737 #define MT_WTBL2_W9_SHORT_GI_40 BIT(17)
738 #define MT_WTBL2_W9_SHORT_GI_80 BIT(18)
739 #define MT_WTBL2_W9_SHORT_GI_160 BIT(19)
745 #define MT_WTBL2_W10_RATE2 GENMASK(23, 12)
765 #define MT_WTBL2_W14_CC_NOISE_SEL BIT(15)
773 #define MT_WTBL1_OR_PSM_WRITE BIT(31)