Lines Matching +full:12 +full:bit
48 * FR_AB_EE_VPD_CFG0_REG_SF(128bit):
54 * FR_AB_EE_VPD_CFG0_REG(128bit):
94 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit):
100 * FR_AB_PCIE_SD_CTL0123_REG(128bit):
162 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit):
168 * FR_AB_PCIE_SD_CTL45_REG(128bit):
198 #define FRF_AB_PCIE_DEQ3_LBN 12
208 * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit):
214 * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit):
234 #define FRF_AB_PCIE_CTCDISABLE_L_LBN 12
248 * FR_AB_HW_INIT_REG_SF(128bit):
254 * FR_AZ_HW_INIT_REG(128bit):
302 * FR_AB_NIC_STAT_REG_SF(128bit):
308 * FR_AB_NIC_STAT_REG(128bit):
334 * FR_AB_GLB_CTL_REG_SF(128bit):
340 * FR_AB_GLB_CTL_REG(128bit):
432 * FR_AZ_IOM_IND_ADR_REG(32bit):
444 * FR_AZ_IOM_IND_DAT_REG(32bit):
454 * FR_AZ_ADR_REGION_REG(128bit):
470 * FR_AZ_INT_EN_REG_KER(128bit):
486 * FR_AZ_INT_EN_REG_CHAR(128bit):
502 * FR_AZ_INT_ADR_REG_KER(128bit):
518 * FR_AZ_INT_ADR_REG_CHAR(128bit):
534 * FR_AA_INT_ACK_KER(32bit):
544 * FR_BZ_INT_ISR0_REG(128bit):
558 * FR_AB_EE_SPI_HCMD_REG(128bit):
574 #define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12
582 * FR_CZ_USR_EV_CFG(32bit):
594 * FR_AB_EE_SPI_HADR_REG(128bit):
606 * FR_AB_EE_SPI_HDATA_REG(128bit):
622 * FR_AB_EE_BASE_PAGE_REG(128bit):
634 * FR_AB_EE_VPD_SW_CNTL_REG(128bit):
648 * FR_AB_EE_VPD_SW_DATA_REG(128bit):
658 * FR_BB_PCIE_CORE_INDIRECT_REG(64bit):
669 #define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12
672 * FR_AB_GPIO_CTL_REG(128bit):
772 #define FRF_AB_GPIO4_IN_LBN 12
796 * FR_AZ_FATAL_INTR_REG_KER(128bit):
830 #define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12
860 * FR_AZ_FATAL_INTR_REG_CHAR(128bit):
894 #define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12
924 * FR_AZ_DP_CTRL_REG(128bit):
931 #define FRF_AZ_FLS_EVQ_ID_WIDTH 12
934 * FR_AZ_MEM_STAT_REG(128bit):
962 * FR_PORT0_CS_DEBUG_REG(128bit):
1007 * FR_AZ_DRIVER_REG(128bit):
1019 * FR_AZ_ALTERA_BUILD_REG(128bit):
1029 * FR_AZ_CSR_SPARE_REG(128bit):
1047 * FR_BZ_DEBUG_DATA_OUT_REG(128bit):
1059 * FR_BZ_EVQ_RPTR_REGP0(32bit):
1067 * FR_AA_EVQ_RPTR_REG_KER(32bit):
1075 * FR_AZ_EVQ_RPTR_REG(32bit):
1084 * FR_BB_EVQ_RPTR_REGP123(32bit):
1098 * FR_BZ_TIMER_COMMAND_REGP0(128bit):
1106 * FR_AA_TIMER_COMMAND_REG_KER(128bit):
1114 * FR_AB_TIMER_COMMAND_REGP123(128bit):
1122 * FR_AA_TIMER_COMMAND_REGP0(128bit):
1132 #define FRF_AB_TC_TIMER_MODE_LBN 12
1137 #define FRF_AB_TC_TIMER_VAL_WIDTH 12
1140 * FR_AZ_DRV_EV_REG(128bit):
1147 #define FRF_AZ_DRV_EV_QID_WIDTH 12
1156 * FR_AZ_EVQ_CTL_REG(128bit):
1174 * FR_AZ_EVQ_CNT1_REG(128bit):
1196 * FR_AZ_EVQ_CNT2_REG(128bit):
1218 * FR_CZ_USR_EV_REG(32bit):
1230 * FR_AZ_BUF_TBL_CFG_REG(128bit):
1240 * FR_AZ_SRM_RX_DC_CFG_REG(128bit):
1252 * FR_AZ_SRM_TX_DC_CFG_REG(128bit):
1262 * FR_AZ_SRM_CFG_REG(128bit):
1268 * FR_AZ_SRM_CFG_REG(128bit):
1286 * FR_AZ_BUF_TBL_UPD_REG(128bit):
1302 * FR_AZ_SRM_UPD_EVQ_REG(128bit):
1309 #define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12
1312 * FR_AZ_SRAM_PARITY_REG(128bit):
1330 * FR_AZ_RX_CFG_REG(128bit):
1394 * FR_AZ_RX_FILTER_CTL_REG(128bit):
1409 #define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12
1415 #define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12
1434 * FR_AZ_RX_FLUSH_DESCQ_REG(128bit):
1443 #define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12
1446 * FR_BZ_RX_DESC_UPD_REGP0(128bit):
1454 * FR_AA_RX_DESC_UPD_REG_KER(128bit):
1462 * FR_AB_RX_DESC_UPD_REGP123(128bit):
1470 * FR_AA_RX_DESC_UPD_REGP0(128bit):
1479 #define FRF_AZ_RX_DESC_WPTR_WIDTH 12
1490 * FR_AZ_RX_DC_CFG_REG(128bit):
1506 * FR_AZ_RX_DC_PF_WM_REG(128bit):
1518 * FR_BZ_RX_RSS_TKEY_REG(128bit):
1536 * FR_AZ_RX_NODESC_DROP_REG(128bit):
1546 * FR_AZ_RX_SELF_RST_REG(128bit):
1564 * FR_AZ_RX_DEBUG_REG(128bit):
1578 * FR_AZ_RX_PUSH_DROP_REG(128bit):
1588 * FR_CZ_RX_RSS_IPV6_REG1(128bit):
1606 * FR_CZ_RX_RSS_IPV6_REG2(128bit):
1624 * FR_CZ_RX_RSS_IPV6_REG3(128bit):
1644 * FR_AZ_TX_FLUSH_DESCQ_REG(128bit):
1650 #define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12
1653 #define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12
1656 * FR_BZ_TX_DESC_UPD_REGP0(128bit):
1664 * FR_AA_TX_DESC_UPD_REG_KER(128bit):
1672 * FR_AB_TX_DESC_UPD_REGP123(128bit):
1680 * FR_AA_TX_DESC_UPD_REGP0(128bit):
1689 #define FRF_AZ_TX_DESC_WPTR_WIDTH 12
1702 * FR_AZ_TX_DC_CFG_REG(128bit):
1715 * FR_AA_TX_CHKSM_CFG_REG(128bit):
1731 * FR_AZ_TX_CFG_REG(128bit):
1773 * FR_AZ_TX_PUSH_DROP_REG(128bit):
1783 * FR_AZ_TX_RESERVED_REG(128bit):
1853 * FR_BZ_TX_PACE_REG(128bit):
1859 * FR_AA_TX_PACE_REG(128bit):
1875 * FR_AZ_TX_PACE_DROP_QID_REG(128bit):
1885 * FR_AB_TX_VLAN_REG(128bit):
1898 #define FRF_AB_TX_VLAN7_WIDTH 12
1904 #define FRF_AB_TX_VLAN6_WIDTH 12
1910 #define FRF_AB_TX_VLAN5_WIDTH 12
1916 #define FRF_AB_TX_VLAN4_WIDTH 12
1922 #define FRF_AB_TX_VLAN3_WIDTH 12
1928 #define FRF_AB_TX_VLAN2_WIDTH 12
1934 #define FRF_AB_TX_VLAN1_WIDTH 12
1937 #define FRF_AB_TX_VLAN0_PORT0_EN_LBN 12
1940 #define FRF_AB_TX_VLAN0_WIDTH 12
1943 * FR_AZ_TX_IPFIL_PORTEN_REG(128bit):
2001 #define FRF_AB_TX_IPFIL6_PORT_EN_LBN 12
2017 * FR_AB_TX_IPFIL_TBL(128bit):
2035 * FR_AB_MD_TXD_REG(128bit):
2045 * FR_AB_MD_RXD_REG(128bit):
2055 * FR_AB_MD_CS_REG(128bit):
2085 * FR_AB_MD_PHY_ADR_REG(128bit):
2095 * FR_AB_MD_ID_REG(128bit):
2107 * FR_AB_MD_STAT_REG(128bit):
2125 * FR_AB_MAC_STAT_DMA_REG(128bit):
2141 * FR_AB_MAC_CTRL_REG(128bit):
2167 * FR_BB_GEN_MODE_REG(128bit):
2183 * FR_AB_MAC_MC_HASH_REG0(128bit):
2201 * FR_AB_MAC_MC_HASH_REG1(128bit):
2219 * FR_AB_GM_CFG1_REG(32bit):
2253 * FR_AB_GM_CFG2_REG(32bit):
2259 #define FRF_AB_GM_PAMBL_LEN_LBN 12
2277 * FR_AB_GM_IPG_REG(32bit):
2293 * FR_AB_GM_HD_REG(32bit):
2309 #define FRF_AB_GM_RTRY_LIMIT_LBN 12
2315 * FR_AB_GM_MAX_FLEN_REG(32bit):
2325 * FR_AB_GM_TEST_REG(32bit):
2341 * FR_AB_GM_ADR1_REG(32bit):
2357 * FR_AB_GM_ADR2_REG(32bit):
2369 * FR_AB_GMF_CFG0_REG(32bit):
2385 #define FRF_AB_GMF_FTFENREQ_LBN 12
2407 * FR_AB_GMF_CFG1_REG(32bit):
2419 * FR_AB_GMF_CFG2_REG(32bit):
2431 * FR_AB_GMF_CFG3_REG(32bit):
2443 * FR_AB_GMF_CFG4_REG(32bit):
2453 * FR_AB_GMF_CFG5_REG(32bit):
2473 * FR_BB_TX_SRC_MAC_TBL(128bit):
2495 * FR_BB_TX_SRC_MAC_CTL_REG(128bit):
2505 #define FRF_BB_TX_DROP_CTR_CLR_LBN 12
2511 * FR_AB_XM_ADR_LO_REG(128bit):
2521 * FR_AB_XM_ADR_HI_REG(128bit):
2531 * FR_AB_XM_GLB_CFG_REG(128bit):
2555 * FR_AB_XM_TX_CFG_REG(128bit):
2581 * FR_AB_XM_RX_CFG_REG(128bit):
2611 * FR_AB_XM_MGT_INT_MASK(128bit):
2631 * FR_AB_XM_FC_REG(128bit):
2657 * FR_AB_XM_PAUSE_TIME_REG(128bit):
2669 * FR_AB_XM_TX_PARAM_REG(128bit):
2685 * FR_AB_XM_RX_PARAM_REG(128bit):
2697 * FR_AB_XM_MGT_INT_MSK_REG(128bit):
2715 * FR_AB_XX_PWR_RST_REG(128bit):
2755 #define FRF_AB_XX_PWRDNA_EN_LBN 12
2777 * FR_AB_XX_SD_CTL_REG(128bit):
2793 #define FRF_AB_XX_LODRVC_LBN 12
2813 * FR_AB_XX_TXDRV_CTL_REG(128bit):
2827 #define FRF_AB_XX_DTXD_LBN 12
2837 * FR_AB_XX_PRBS_CTL_REG(128bit):
2871 #define FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12
2893 * FR_AB_XX_PRBS_CHK_REG(128bit):
2907 #define FRF_AB_XX_CH3_ERR_CHK_LBN 12
2935 * FR_AB_XX_PRBS_ERR_REG(128bit):
2951 * FR_AB_XX_CORE_STAT_REG(128bit):
2995 #define FRF_AB_XX_COMMA_DET_CH0_LBN 12
3023 * FR_AA_RX_DESC_PTR_TBL_KER(128bit):
3031 * FR_AZ_RX_DESC_PTR_TBL(128bit):
3053 #define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12
3055 #define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12
3059 #define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12
3078 * FR_AA_TX_DESC_PTR_TBL_KER(128bit):
3086 * FR_AZ_TX_DESC_PTR_TBL(128bit):
3116 #define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12
3118 #define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12
3122 #define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12
3139 * FR_AA_EVQ_PTR_TBL_KER(128bit):
3147 * FR_AZ_EVQ_PTR_TBL(128bit):
3177 * FR_AA_BUF_HALF_TBL_KER(64bit):
3185 * FR_AZ_BUF_HALF_TBL(64bit):
3197 #define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12
3198 #define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12
3201 #define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12
3204 * FR_AA_BUF_FULL_TBL_KER(64bit):
3212 * FR_AZ_BUF_FULL_TBL(64bit):
3242 * FR_AZ_RX_FILTER_TBL0(128bit):
3250 * FR_AB_RX_FILTER_TBL1(128bit):
3265 #define FRF_AZ_RXQ_ID_WIDTH 12
3276 * FR_CZ_RX_MAC_FILTER_TBL0(128bit):
3291 #define FRF_CZ_RMFT_RXQ_ID_WIDTH 12
3294 #define FRF_CZ_RMFT_DEST_MAC_LBN 12
3296 #define FRF_CZ_RMFT_DEST_MAC_DW0_LBN 12
3301 #define FRF_CZ_RMFT_VLAN_ID_WIDTH 12
3304 * FR_AZ_TIMER_TBL(128bit):
3329 #define FRF_AB_TIMER_MODE_LBN 12
3338 #define FRF_AB_TIMER_VAL_WIDTH 12
3341 * FR_BZ_TX_PACE_TBL(128bit):
3350 * FR_AA_TX_PACE_TBL(128bit):
3362 * FR_BZ_RX_INDIRECTION_TBL(7bit):
3374 * FR_CZ_TX_FILTER_TBL0(128bit):
3385 #define FRF_CZ_TIFT_TXQ_ID_WIDTH 12
3396 * FR_CZ_TX_MAC_FILTER_TBL0(128bit):
3405 #define FRF_CZ_TMFT_TXQ_ID_WIDTH 12
3408 #define FRF_CZ_TMFT_SRC_MAC_LBN 12
3410 #define FRF_CZ_TMFT_SRC_MAC_DW0_LBN 12
3415 #define FRF_CZ_TMFT_VLAN_ID_WIDTH 12
3418 * FR_CZ_MC_TREG_SMEM(32bit):
3430 * FR_BB_MSIX_VECTOR_TABLE(128bit):
3438 * FR_CZ_MSIX_VECTOR_TABLE(128bit):
3458 * FR_BB_MSIX_PBA_TABLE(32bit):
3459 * MSIX Pending Bit Array
3466 * FR_CZ_MSIX_PBA_TABLE(32bit):
3467 * MSIX Pending Bit Array
3478 * FR_AZ_SRM_DBG_REG(64bit):
3496 * FR_AA_INT_ACK_CHAR(32bit):
3539 #define FSF_AA_GLB_EV_RX_RECOVERY_LBN 12
3612 #define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12
3615 #define FSF_AZ_RX_EV_DESC_PTR_WIDTH 12
3631 #define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12
3648 #define FSF_AZ_TX_EV_COMP_LBN 12
3651 #define FSF_AZ_TX_EV_DESC_PTR_WIDTH 12
3699 #define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12
3702 #define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12