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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-mtk-tphy.txt5 controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
23 the child's base address to 0, the physical address
72 reg = <0 0x11290000 0 0x800>;
78 reg = <0 0x11290800 0 0x100>;
85 reg = <0 0x11290800 0 0x700>;
92 reg = <0 0x11291000 0 0x100>;
113 phy-names = "usb2-0", "usb3-0";
122 shared 0x0000 SPLLC
123 0x0100 FMREG
124 u2 port0 0x0800 U2PHY_COM
[all …]
H A Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap3430es1-clocks.dtsi9 #clock-cells = <0>;
12 reg = <0x0b10>;
13 ti,bit-shift = <0>;
17 #clock-cells = <0>;
21 reg = <0x0b40>;
26 #clock-cells = <0>;
34 #clock-cells = <0>;
37 reg = <0x0b00>;
42 #clock-cells = <0>;
45 reg = <0x0b00>;
[all …]
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi9 #clock-cells = <0>;
17 #clock-cells = <0>;
26 #clock-cells = <0>;
29 reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
35 #clock-cells = <0>;
39 reg = <0x0d50>;
44 #clock-cells = <0>;
48 reg = <0x0b00>;
52 #clock-cells = <0>;
60 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dcavium-mdio.txt15 - #size-cells: Must be <0>. MDIO addresses have no size component.
23 #size-cells = <0>;
24 reg = <0x11800 0x00001800 0x0 0x40>;
26 ethernet-phy@0 {
28 reg = <0>;
58 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
59 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
60 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
65 #size-cells = <0>;
66 reg = <0x87e0 0x05003800 0x0 0x30>;
[all …]
/freebsd/sys/dev/amdsbwd/
H A Damd_chipset.h36 * a PCI Device ID of 0x43851002 and a revision less than 0x40
39 * Device ID of 0x43851002 and a revision greater than or equal to 0x40
40 * o FCHs where the controller has an ID of 0x780b1022 and a revision less
41 * than 0x41 (various variants of "Hudson" and "Bolton" as well as FCHs
43 * o FCHs where the controller has an ID of 0x790b1022 and a revision less
44 * than 0x49
46 * o FCHs where the SMBus controller device has a PCI Device ID of 0x780b1022
47 * and a revision greater than or equal to 0x41 (integrated into "Mullins"
49 * o FCHs where the controller has an ID of 0x790b1022 and a revision greater
50 * than or equal to 0x49 (integrated into "Carrizo" processors, code named
[all …]
/freebsd/sys/dev/eqos/
H A Dif_eqos_reg.h38 #define GMAC_MAC_CONFIGURATION 0x0000
49 #define GMAC_MAC_CONFIGURATION_RE (1U << 0)
50 #define GMAC_MAC_EXT_CONFIGURATION 0x0004
51 #define GMAC_MAC_PACKET_FILTER 0x0008
59 #define GMAC_MAC_PACKET_FILTER_PR (1U << 0)
60 #define GMAC_MAC_WATCHDOG_TIMEOUT 0x000C
61 #define GMAC_MAC_HASH_TABLE_REG0 0x0010
62 #define GMAC_MAC_HASH_TABLE_REG1 0x0014
63 #define GMAC_MAC_VLAN_TAG 0x0050
64 #define GMAC_MAC_Q0_TX_FLOW_CTRL 0x0070
[all …]
/freebsd/sys/arm/xilinx/
H A Dzy7_slcr.h43 #define ZY7_SCLR_SCL 0x0000
44 #define ZY7_SLCR_LOCK 0x0004
45 #define ZY7_SLCR_LOCK_MAGIC 0x767b
46 #define ZY7_SLCR_UNLOCK 0x0008
47 #define ZY7_SLCR_UNLOCK_MAGIC 0xdf0d
48 #define ZY7_SLCR_LOCKSTA 0x000c
51 #define ZY7_SLCR_ARM_PLL_CTRL 0x0100
52 #define ZY7_SLCR_DDR_PLL_CTRL 0x0104
53 #define ZY7_SLCR_IO_PLL_CTRL 0x0108
54 #define ZY7_SLCR_PLL_CTRL_RESET (1 << 0)
[all …]
/freebsd/sys/dev/iavf/
H A Diavf_adminq_cmd.h43 #define IAVF_FW_API_VERSION_MAJOR 0x0001
44 #define IAVF_FW_API_VERSION_MINOR_X722 0x0006
45 #define IAVF_FW_API_VERSION_MINOR_X710 0x0007
52 #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
54 #define IAVF_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
81 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
86 #define IAVF_AQ_FLAG_DD_SHIFT 0
98 #define IAVF_AQ_FLAG_DD (1 << IAVF_AQ_FLAG_DD_SHIFT) /* 0x1 */
99 #define IAVF_AQ_FLAG_CMP (1 << IAVF_AQ_FLAG_CMP_SHIFT) /* 0x2 */
100 #define IAVF_AQ_FLAG_ERR (1 << IAVF_AQ_FLAG_ERR_SHIFT) /* 0x4 */
[all …]
/freebsd/sys/dev/dwc/
H A Dif_dwc_rk.c56 #define RK3328_GRF_MAC_CON0 0x0900
57 #define MAC_CON0_GMAC2IO_TX_DL_CFG_MASK 0x7F
58 #define MAC_CON0_GMAC2IO_TX_DL_CFG_SHIFT 0
59 #define MAC_CON0_GMAC2IO_RX_DL_CFG_MASK 0x7F
62 #define RK3328_GRF_MAC_CON1 0x0904
63 #define MAC_CON1_GMAC2IO_GMAC_TXCLK_DLY_ENA (1 << 0)
66 #define MAC_CON1_GMAC2IO_GMII_CLK_SEL_125 (0 << 11)
76 #define MAC_CON1_GMAC2IO_RMII_CLK_SEL_2_5 (0 << 7)
79 #define MAC_CON1_GMAC2IO_MAC_SPEED_10 (0 << 2)
80 #define RK3328_GRF_MAC_CON2 0x0908
[all …]
/freebsd/sys/dev/mii/
H A Dbrgphyreg.h42 #define BRGPHY_MII_BMCR 0x00
43 #define BRGPHY_BMCR_RESET 0x8000
44 #define BRGPHY_BMCR_LOOP 0x4000
45 #define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
46 #define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
47 #define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
48 #define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
49 #define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
50 #define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
51 #define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
[all …]
/freebsd/sys/dev/bwn/
H A Dif_bwn_phy_lp.c155 { 0x6f, 0x3c, 0x3c, 0x4, 0x5, 0x5, 0x5, 0x5, 0x77, 0x80, 0x80, 0x70 },
156 { 0x6f, 0x2c, 0x2c, 0x4, 0x5, 0x5, 0x5, 0x5, 0x77, 0x80, 0x80, 0x70 },
157 { 0x6f, 0x1c, 0x1c, 0x4, 0x5, 0x5, 0x5, 0x5, 0x77, 0x80, 0x80, 0x70 },
158 { 0x6e, 0x1c, 0x1c, 0x4, 0x5, 0x5, 0x5, 0x5, 0x77, 0x80, 0x80, 0x70 },
159 { 0x6e, 0xc, 0xc, 0x4, 0x5, 0x5, 0x5, 0x5, 0x77, 0x80, 0x80, 0x70 },
160 { 0x6a, 0xc, 0xc, 0, 0x2, 0x5, 0xd, 0xd, 0x77, 0x80, 0x20, 0 },
161 { 0x6a, 0xc, 0xc, 0, 0x1, 0x5, 0xd, 0xc, 0x77, 0x80, 0x20, 0 },
162 { 0x6a, 0xc, 0xc, 0, 0x1, 0x4, 0xc, 0xc, 0x77, 0x80, 0x20, 0 },
163 { 0x69, 0xc, 0xc, 0, 0x1, 0x4, 0xc, 0xc, 0x77, 0x70, 0x20, 0 },
164 { 0x69, 0xc, 0xc, 0, 0x1, 0x4, 0xb, 0xc, 0x77, 0x70, 0x20, 0 },
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/freebsd/sys/dev/usb/controller/
H A Ddwc_otgreg.h32 #define DOTG_GOTGCTL 0x0000
33 #define DOTG_GOTGINT 0x0004
34 #define DOTG_GAHBCFG 0x0008
35 #define DOTG_GUSBCFG 0x000C
36 #define DOTG_GRSTCTL 0x0010
37 #define DOTG_GINTSTS 0x0014
38 #define DOTG_GINTMSK 0x0018
39 #define DOTG_GRXSTSRD 0x001C
40 #define DOTG_GRXSTSRH 0x001C
41 #define DOTG_GRXSTSPD 0x0020
[all …]
/freebsd/sys/dev/ixl/
H A Di40e_adminq_cmd.h44 #define I40E_FW_API_VERSION_MAJOR 0x0001
45 #define I40E_FW_API_VERSION_MINOR_X722 0x000C
46 #define I40E_FW_API_VERSION_MINOR_X710 0x000F
53 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
55 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
57 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
59 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A
86 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
91 #define I40E_AQ_FLAG_DD_SHIFT 0
103 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
[all …]
/freebsd/sys/dev/sound/pci/hda/
H A Dhdac.h40 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))
43 #define INTEL_VENDORID 0x8086
44 #define HDA_INTEL_CMLKLP HDA_MODEL_CONSTRUCT(INTEL, 0x02c8)
45 #define HDA_INTEL_CMLKH HDA_MODEL_CONSTRUCT(INTEL, 0x06c8)
46 #define HDA_INTEL_OAK HDA_MODEL_CONSTRUCT(INTEL, 0x080a)
47 #define HDA_INTEL_BAY HDA_MODEL_CONSTRUCT(INTEL, 0x0f04)
48 #define HDA_INTEL_HSW1 HDA_MODEL_CONSTRUCT(INTEL, 0x0a0c)
49 #define HDA_INTEL_HSW2 HDA_MODEL_CONSTRUCT(INTEL, 0x0c0c)
50 #define HDA_INTEL_HSW3 HDA_MODEL_CONSTRUCT(INTEL, 0x0d0c)
51 #define HDA_INTEL_BDW1 HDA_MODEL_CONSTRUCT(INTEL, 0x160c)
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Ddebug.c84 return 0; in rtw_debugfs_close()
122 seq_printf(m, "reg 0x%03x: 0x%02x\n", addr, val); in rtw_debugfs_get_read_reg()
126 seq_printf(m, "reg 0x%03x: 0x%04x\n", addr, val); in rtw_debugfs_get_read_reg()
130 seq_printf(m, "reg 0x%03x: 0x%08x\n", addr, val); in rtw_debugfs_get_read_reg()
133 return 0; in rtw_debugfs_get_read_reg()
151 seq_printf(m, "rf_read path:%d addr:0x%08x mask:0x%08x val=0x%08x\n", in rtw_debugfs_get_rf_read()
154 return 0; in rtw_debugfs_get_rf_read()
166 return 0; in rtw_debugfs_get_fix_rate()
170 return 0; in rtw_debugfs_get_fix_rate()
179 memset(tmp, 0, size); in rtw_debugfs_copy_from_user()
[all …]
/freebsd/sys/dev/sk/
H A Dif_skreg.h54 #define SK_GENESIS 0x0A
55 #define SK_YUKON 0xB0
56 #define SK_YUKON_LITE 0xB1
57 #define SK_YUKON_LP 0xB2
58 #define SK_YUKON_FAMILY(x) ((x) & 0xB0)
61 #define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */
62 #define SK_YUKON_LITE_REV_A1 0x3
63 #define SK_YUKON_LITE_REV_A3 0x7
68 #define VENDORID_SK 0x1148
73 #define VENDORID_MARVELL 0x11AB
[all …]
/freebsd/sys/dev/e1000/
H A De1000_defines.h44 #define E1000_WUC_APME 0x00000001 /* APM Enable */
45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
46 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
47 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
48 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
51 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
54 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
55 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
[all …]
/freebsd/sys/dev/igc/
H A Digc_defines.h16 #define IGC_WUC_APME 0x00000001 /* APM Enable */
17 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
18 #define IGC_WUC_PME_STATUS 0x00000004 /* PME Status */
19 #define IGC_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
20 #define IGC_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
23 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
24 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
25 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
26 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
27 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
[all …]
/freebsd/sys/dev/isci/scil/
H A Dscu_registers.h91 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_SHIFT (0UL)
92 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_MASK (0x00000FFFUL)
94 #define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_MASK (0x0000F000UL)
96 #define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_MASK (0x00030000UL)
98 #define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_MASK (0x00FC0000UL)
99 #define SMU_POST_CONTEXT_PORT_RESERVED_MASK (0xFF000000UL)
106 #define SMU_INTERRUPT_STATUS_COMPLETION_MASK (0x80000000UL)
108 #define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_MASK (0x00000002UL)
109 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_SHIFT (0UL)
110 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_MASK (0x00000001UL)
[all …]
/freebsd/sys/dev/bxe/
H A Decore_reg.h35 (0x1<<0)
37 (0x1<<2)
39 (0x1<<5)
41 (0x1<<3)
43 (0x1<<4)
45 (0x1<<1)
47 0x1100bcUL
49 0x1101c0UL
51 0x1101d8UL
53 0x1101d0UL
[all …]
/freebsd/share/i18n/csmapper/CNS/
H A DCNS11643-6%UCS@SIP.src5 SRC_ZONE 0x21-0x7E / 0x21-0x7E / 8
7 DST_ILSEQ 0xFFFE
13 # Unicode version: 5.0.0
47 0x2121 = 0xF802
48 0x2122 = 0x0062
49 0x2124 = 0x0088
50 0x2125 = 0x00D0
51 0x2126 = 0x00CF
52 0x2127 = 0x011E
53 0x2128 = 0x011F
[all …]
H A DUCS@SIP%CNS11643-6.src5 SRC_ZONE 0x0003 - 0xFA17
7 DST_INVALID 0xFFFF
13 # Unicode version: 5.0.0
47 0x0003 = 0x212F
48 0x0004 = 0x212D
49 0x0005 = 0x212E
50 0x0007 = 0x2142
51 0x0008 = 0x2143
52 0x0012 = 0x222B
53 0x0018 = 0x2340
[all …]
/freebsd/sys/dev/usb/
H A Dusbdevs50 * #define USB_VENDOR_VNDR 0x????
51 * #define USB_PRODUCT_VNDR_PRDCT 0x????
57 vendor UNKNOWN1 0x0053 Unknown vendor
58 vendor UNKNOWN2 0x0105 Unknown vendor
59 vendor EGALAX2 0x0123 eGalax, Inc.
60 vendor CHIPSBANK 0x0204 Chipsbank Microelectronics Co.
61 vendor HUMAX 0x02ad HUMAX
62 vendor QUAN 0x01e1 Quan
63 vendor LTS 0x0386 LTS
64 vendor BWCT 0x03da Bernd Walter Computer Technology
[all …]

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