56 #define	RK3328_GRF_MAC_CON0		0x0900
57 #define	 MAC_CON0_GMAC2IO_TX_DL_CFG_MASK	0x7F
58 #define	 MAC_CON0_GMAC2IO_TX_DL_CFG_SHIFT	0
59 #define	 MAC_CON0_GMAC2IO_RX_DL_CFG_MASK	0x7F
62 #define	RK3328_GRF_MAC_CON1		0x0904
63 #define	 MAC_CON1_GMAC2IO_GMAC_TXCLK_DLY_ENA	(1 << 0)
66 #define	 MAC_CON1_GMAC2IO_GMII_CLK_SEL_125	(0 << 11)
76 #define	 MAC_CON1_GMAC2IO_RMII_CLK_SEL_2_5	(0 << 7)
79 #define	 MAC_CON1_GMAC2IO_MAC_SPEED_10		(0 << 2)
80 #define	RK3328_GRF_MAC_CON2		0x0908
81 #define	RK3328_GRF_MACPHY_CON0		0x0B00
86 #define	RK3328_GRF_MACPHY_CON1		0x0B04
89 #define	RK3328_GRF_MACPHY_CON2		0x0B08
90 #define	RK3328_GRF_MACPHY_CON3		0x0B0C
91 #define	RK3328_GRF_MACPHY_STATUS	0x0B10
93 #define	RK3399_GRF_SOC_CON5		0xc214
95 #define	 SOC_CON5_GMAC_CLK_SEL_125		(0 << 4)
98 #define	RK3399_GRF_SOC_CON6		0xc218
100 #define	 SOC_CON6_TX_DL_CFG_MASK		0x7F
101 #define	 SOC_CON6_TX_DL_CFG_SHIFT		0
102 #define	 SOC_CON6_RX_DL_CFG_MASK		0x7F
170 	{NULL,			 0}
200 	reg = 0xffff << 16;  in rk3328_set_delays()
259 	return (0);  in rk3328_set_speed()
312 	reg = 0xFFFF << 16;  in rk3399_set_delays()
345 	return (0);  in rk3399_set_speed()
358 	rv = sysctl_handle_int(oidp, &rxtx, 0, req);  in if_dwc_rk_sysctl_delays()
359 	if (rv != 0 || req->newptr == NULL)  in if_dwc_rk_sysctl_delays()
361 	sc->tx_delay = rxtx & 0xff;  in if_dwc_rk_sysctl_delays()
362 	sc->rx_delay = (rxtx >> 8) & 0xff;  in if_dwc_rk_sysctl_delays()
367 	return (0);  in if_dwc_rk_sysctl_delays()
380 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, sc, 0,  in if_dwc_rk_init_sysctl()
383 	return (0);  in if_dwc_rk_init_sysctl()
392 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)  in if_dwc_rk_probe()
408 	if (clk_get_by_ofw_name(dev, 0, "mac_clk_tx", &sc->mac_clk_tx) != 0) {  in if_dwc_rk_init_clocks()
413 	if (clk_get_by_ofw_name(dev, 0, "aclk_mac", &sc->aclk_mac) != 0) {  in if_dwc_rk_init_clocks()
418 	if (clk_get_by_ofw_name(dev, 0, "pclk_mac", &sc->pclk_mac) != 0) {  in if_dwc_rk_init_clocks()
424 	clk_get_by_ofw_name(dev, 0, "clk_mac_speed", &sc->clk_mac_speed);  in if_dwc_rk_init_clocks()
427 		if (clk_get_by_ofw_name(dev, 0, "mac_clk_rx", &sc->mac_clk_rx) != 0) {  in if_dwc_rk_init_clocks()
432 		if (clk_get_by_ofw_name(dev, 0, "clk_mac_ref", &sc->clk_mac_ref) != 0) {  in if_dwc_rk_init_clocks()
438 			if (clk_get_by_ofw_name(dev, 0, "clk_mac_refout", &sc->clk_mac_refout) != 0) {  in if_dwc_rk_init_clocks()
443 			clk_set_freq(sc->clk_stmmaceth, 50000000, 0);  in if_dwc_rk_init_clocks()
447 	if ((sc->phy_node != 0) && sc->integrated_phy) {  in if_dwc_rk_init_clocks()
448 		if (clk_get_by_ofw_index(dev, sc->phy_node, 0, &sc->clk_phy) != 0) {  in if_dwc_rk_init_clocks()
454 			clk_set_freq(sc->clk_phy, 50000000, 0);  in if_dwc_rk_init_clocks()
479 	return (0);  in if_dwc_rk_init_clocks()
499 	    "rockchip,grf", &sc->grf) != 0) {  in if_dwc_rk_init()
504 	if (OF_getencprop(node, "tx_delay", &tx, sizeof(tx)) <= 0)  in if_dwc_rk_init()
505 		tx = 0x30;  in if_dwc_rk_init()
506 	if (OF_getencprop(node, "rx_delay", &rx, sizeof(rx)) <= 0)  in if_dwc_rk_init()
507 		rx = 0x10;  in if_dwc_rk_init()
513 		if (strcmp(clock_in_out, "input") == 0)  in if_dwc_rk_init()
521 	    sizeof(phy_handle)) > 0)  in if_dwc_rk_init()
542 	if (err != 0)  in if_dwc_rk_init()
545 	if (regulator_get_by_ofw_property(sc->base.dev, 0,  in if_dwc_rk_init()
546 		            "phy-supply", &phy_supply) == 0) {  in if_dwc_rk_init()
566 		SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON2, 0xffff1234);  in if_dwc_rk_init()
567 		SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON3, 0x003f0035);  in if_dwc_rk_init()
569 		if (hwreset_get_by_ofw_idx(dev, sc->phy_node, 0, &phy_reset)  == 0) {  in if_dwc_rk_init()
577 	return (0);  in if_dwc_rk_init()
588 	if ((rv = clk_get_freq(sc->pclk_mac, &freq)) != 0)  in if_dwc_rk_mii_clk()
618 	return (0);  in if_dwc_rk_set_speed()
635 DRIVER_MODULE(dwc_rk, simplebus, dwc_rk_driver, 0, 0);