| /freebsd/sys/contrib/device-tree/src/arm/broadcom/ |
| H A D | bcm53573.dtsi | 26 #size-cells = <0>; 28 cpu@0 { 31 reg = <0x0>; 37 ranges = <0x00000000 0x18310000 0x00008000>; 44 #address-cells = <0>; 46 reg = <0x1000 0x1000>, 47 <0x200 [all...] |
| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | mvebu-pci.txt | 23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s 32 registers area. This range entry translates the '0x82000000 0 r' PCI 33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part 34 of the internal register window (as identified by MBUS_ID(0xf0, 35 0x01)). 39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0 79 value is 0. 99 bus-range = <0x00 0xff>; 103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ [all …]
|
| /freebsd/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | armada-xp-mv78460.dtsi | 28 #size-cells = <0>; 31 cpu@0 { 34 reg = <0>; 35 clocks = <&cpuclk 0>; 66 * MV78460 has 4 PCIe units Gen2.0: Two units can be 79 bus-range = <0x00 0xff>; 82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ [all …]
|
| H A D | armada-xp-mv78260.dtsi | 27 #size-cells = <0>; 30 cpu@0 { 33 reg = <0>; 34 clocks = <&cpuclk 0>; 49 * MV78260 has 3 PCIe units Gen2.0: Two units can be 62 bus-range = <0x00 0xff>; 65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ [all …]
|
| H A D | armada-380.dtsi | 20 #size-cells = <0>; 23 cpu@0 { 26 reg = <0>; 46 bus-range = <0x00 0xff>; 49 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 50 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 51 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 52 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 53 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 54 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ [all …]
|
| H A D | armada-385.dtsi | 20 #size-cells = <0>; 23 cpu@0 { 26 reg = <0>; 45 bus-range = <0x00 0xff>; 48 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 49 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 50 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 51 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 52 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 53 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ [all …]
|
| H A D | armada-xp-mv78230.dtsi | 26 #size-cells = <0>; 29 cpu@0 { 32 reg = <0>; 33 clocks = <&cpuclk 0>; 48 * MV78230 has 2 PCIe units Gen2.0: One unit can be 61 bus-range = <0x00 0xff>; 64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ [all …]
|
| H A D | kirkwood-6282.dtsi | 12 bus-range = <0x00 0xff>; 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 17 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 18 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 19 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 20 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ 21 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; 23 pcie0: pcie@1,0 { 25 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; [all …]
|
| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | omap4460.dtsi | 12 cpu0: cpu@0 { 32 reg = <0x4a002260 0x4 33 0x4a00232C 0x4 34 0x4a002378 0x18>; 36 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */ 39 #thermal-sensor-cells = <0>; 45 reg = <0x4a307bd [all...] |
| /freebsd/sys/contrib/device-tree/src/nios2/ |
| H A D | 3c120_devboard.dts | 18 #size-cells = <0>; 20 cpu: cpu@0 { 23 reg = <0x00000000>; 38 altr,reset-addr = <0xc2800000>; 39 altr,fast-tlb-miss-addr = <0xc7fff400>; 40 altr,exception-addr = <0xd0000020>; 46 memory@0 { 48 reg = <0x10000000 0x08000000>, 49 <0x07fff400 0x00000400>; 52 sopc@0 { [all …]
|
| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | fsl-ls2088a.dtsi | 23 cpu0: cpu@0 { 26 reg = <0x0>; 27 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 36 reg = <0x1>; 37 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 46 reg = <0x100>; 56 reg = <0x101>; 66 reg = <0x200>; 76 reg = <0x201>; 86 reg = <0x300>; [all …]
|
| H A D | fsl-ls2080a.dtsi | 23 cpu0: cpu@0 { 26 reg = <0x0>; 27 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 36 reg = <0x1>; 37 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 46 reg = <0x100>; 56 reg = <0x101>; 66 reg = <0x200>; 76 reg = <0x201>; 86 reg = <0x300>; [all …]
|
| /freebsd/sys/dev/lge/ |
| H A D | if_lgereg.h | 37 #define LGE_MODE1 0x00 /* CSR00 */ 38 #define LGE_MODE2 0x04 /* CSR01 */ 39 #define LGE_PPTXBUF_IDX 0x08 /* CSR02 */ 40 #define LGE_PRODID 0x0C /* CSR03 */ 41 #define LGE_PPTXBUF_ADDR_LO 0x10 /* CSR04 */ 42 #define LGE_PPTXBUF_ADDR_HI 0x14 /* CSR05 */ 43 #define LGE_RSVD0 0x18 /* CSR06 */ 44 #define LGE_PPRXBUF_IDX 0x1C /* CSR07 */ 45 #define LGE_PPRXBUF_ADDR_LO 0x20 /* CSR08 */ 46 #define LGE_PPRXBUF_ADDR_HI 0x24 /* CSR09 */ [all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | mvebu-mbus.txt | 65 pcie-mem-aperture = <0xe0000000 0x8000000>; 66 pcie-io-aperture = <0xe8000000 0x100000>; 73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; 87 0xSIAA0000 0x00oooooo 91 S = 0x0 for a MBus valid window 92 S = 0xf for a non-valid window (see below) 94 If S = 0x0, then: 99 If S = 0xf, then: 105 (S = 0x0), an address decoding window is allocated. On the other side, 106 entries for translation that do not correspond to valid windows (S = 0xf) [all …]
|
| /freebsd/sys/dev/mpt/ |
| H A D | mpt_reg.h | 69 #define MPT_OFFSET_DOORBELL 0x00 70 #define MPT_OFFSET_SEQUENCE 0x04 71 #define MPT_OFFSET_DIAGNOSTIC 0x08 72 #define MPT_OFFSET_TEST 0x0C 73 #define MPT_OFFSET_DIAG_DATA 0x10 74 #define MPT_OFFSET_DIAG_ADDR 0x14 75 #define MPT_OFFSET_INTR_STATUS 0x30 76 #define MPT_OFFSET_INTR_MASK 0x34 77 #define MPT_OFFSET_REQUEST_Q 0x40 78 #define MPT_OFFSET_REPLY_Q 0x44 [all …]
|
| /freebsd/sys/dev/dc/ |
| H A D | if_dcreg.h | 39 #define DC_BUSCTL 0x00 /* bus control */ 40 #define DC_TXSTART 0x08 /* tx start demand */ 41 #define DC_RXSTART 0x10 /* rx start demand */ 42 #define DC_RXADDR 0x18 /* rx descriptor list start addr */ 43 #define DC_TXADDR 0x20 /* tx descriptor list start addr */ 44 #define DC_ISR 0x28 /* interrupt status register */ 45 #define DC_NETCFG 0x30 /* network config register */ 46 #define DC_IMR 0x38 /* interrupt mask */ 47 #define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ 48 #define DC_SIO 0x48 /* MII and ROM/EEPROM access */ [all …]
|
| /freebsd/sys/dev/bge/ |
| H A D | if_bgereg.h | 54 * device register space at offset 0x8000 to read any 32K chunk 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 64 #define BGE_PAGE_ZERO 0x00000000 65 #define BGE_PAGE_ZERO_END 0x000000FF 66 #define BGE_SEND_RING_RCB 0x00000100 67 #define BGE_SEND_RING_RCB_END 0x000001FF 68 #define BGE_RX_RETURN_RING_RCB 0x00000200 69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70 #define BGE_STATS_BLOCK 0x00000300 71 #define BGE_STATS_BLOCK_END 0x00000AFF [all …]
|
| /freebsd/contrib/bearssl/src/symcipher/ |
| H A D | des_tab.c | 30 * order (rightmost bit is 0). 36 4, 14, 18, 8, 17, 0, 19 46 24, 7, 13, 0, 21, 17, 1 53 0x00808200, 0x00000000, 0x00008000, 0x00808202, 54 0x00808002, 0x00008202, 0x00000002, 0x00008000, 55 0x00000200, 0x00808200, 0x00808202, 0x00000200, 56 0x00800202, 0x00808002, 0x00800000, 0x00000002, 57 0x00000202, 0x00800200, 0x00800200, 0x00008200, 58 0x00008200, 0x00808000, 0x00808000, 0x00800202, 59 0x00008002, 0x00800002, 0x00800002, 0x00008002, [all …]
|
| /freebsd/sys/x86/include/ |
| H A D | apicreg.h | 40 * is 0xfee00000. 55 * 0A0 Processor Priority Register R 56 * 0B0 EOI Register W 57 * 0C0 RRR Remote read R 58 * 0D0 Logical Destination R/W 59 * 0E0 Destination Format Register 0..27 R; 28..31 R/W 60 * 0F0 SVR Spurious Interrupt Vector Reg. 0..3 R; 4..9 R/W 93 * 300 ICR_LOW Interrupt Command Reg. (0-31) R/W 195 LAPIC_ID = 0x2, 196 LAPIC_VERSION = 0x3, [all …]
|
| H A D | specialreg.h | 38 #define CR0_PE 0x00000001 /* Protected mode Enable */ 39 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 40 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 41 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 42 #define CR0_PG 0x80000000 /* PaGing enable */ 47 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 48 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 51 #define CR0_NW 0x20000000 /* Not Write-through */ 52 #define CR0_CD 0x40000000 /* Cache Disable */ [all …]
|
| /freebsd/crypto/libecc/src/examples/hash/ |
| H A D | tdes.c | 24 } while( 0 ) 34 } while( 0 ) 40 0x01010400, 0x00000000, 0x00010000, 0x01010404, 41 0x01010004, 0x00010404, 0x00000004, 0x00010000, 42 0x00000400, 0x01010400, 0x01010404, 0x00000400, 43 0x01000404, 0x01010004, 0x01000000, 0x00000004, 44 0x00000404, 0x01000400, 0x01000400, 0x00010400, 45 0x00010400, 0x01010000, 0x01010000, 0x01000404, 46 0x00010004, 0x01000004, 0x01000004, 0x00010004, 47 0x00000000, 0x00000404, 0x00010404, 0x01000000, [all …]
|
| /freebsd/sys/dev/igc/ |
| H A D | igc_base.h | 43 #define IGC_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 44 #define IGC_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 45 #define IGC_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 46 #define IGC_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 47 #define IGC_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 48 #define IGC_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 49 #define IGC_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 50 #define IGC_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 51 #define IGC_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 52 #define IGC_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */ [all …]
|
| /freebsd/sys/dev/nge/ |
| H A D | if_ngereg.h | 36 #define NGE_CSR 0x00 37 #define NGE_CFG 0x04 38 #define NGE_MEAR 0x08 39 #define NGE_PCITST 0x0C 40 #define NGE_ISR 0x10 41 #define NGE_IMR 0x14 42 #define NGE_IER 0x18 43 #define NGE_IHR 0x1C 44 #define NGE_TX_LISTPTR_LO 0x20 45 #define NGE_TX_LISTPTR_HI 0x24 [all …]
|
| /freebsd/sys/powerpc/include/ |
| H A D | hid.h | 35 #define HID0_RADIX 0x0080000000000000 /* Enable Radix page tables (POWER9) */ 37 #define HID0_EMCP 0x80000000 /* Enable machine check pin */ 38 #define HID0_DBP 0x40000000 /* Disable 60x bus parity generation */ 39 #define HID0_EBA 0x20000000 /* Enable 60x bus address parity checking */ 40 #define HID0_EBD 0x10000000 /* Enable 60x bus data parity checking */ 41 #define HID0_BCLK 0x08000000 /* CLK_OUT clock type selection */ 42 #define HID0_EICE 0x04000000 /* Enable ICE output */ 43 #define HID0_ECLK 0x02000000 /* CLK_OUT clock type selection */ 44 #define HID0_PAR 0x01000000 /* Disable precharge of ARTRY */ 45 #define HID0_STEN 0x01000000 /* Software table search enable (7450) */ [all …]
|
| /freebsd/sys/dev/bhnd/cores/pmu/ |
| H A D | bhnd_pmureg.h | 29 (((_value) & _flag) != 0) 43 #define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */ 55 #define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */ 56 #define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */ 57 #define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */ 58 #define BHND_CCS_FORCE_MASK 0x0000000F 60 #define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */ 61 #define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */ 62 #define BHND_CCS_AREQ_MASK 0x00000018 64 #define BHND_CCS_FORCEHWREQOFF 0x00000020 /**< Force HW Clock Request Off */ [all …]
|