Lines Matching +full:0 +full:x00002000

12 			bus-range = <0x00 0xff>;
15 			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16 			        0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
17 				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
18 				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
19 				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
20 				0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0       1 0 /* Port 1.0 MEM */
21 				0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0       1 0 /* Port 1.0 IO  */>;
23 			pcie0: pcie@1,0 {
25 				assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
26 				reg = <0x0800 0 0 0 0>;
30 				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
31 					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
32 				bus-range = <0x00 0xff>;
35 				interrupt-map-mask = <0 0 0 7>;
36 				interrupt-map = <0 0 0 1 &pcie0_intc 0>,
37 						<0 0 0 2 &pcie0_intc 1>,
38 						<0 0 0 3 &pcie0_intc 2>,
39 						<0 0 0 4 &pcie0_intc 3>;
40 				marvell,pcie-port = <0>;
41 				marvell,pcie-lane = <0>;
51 			pcie1: pcie@2,0 {
53 				assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
54 				reg = <0x1000 0 0 0 0>;
58 				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
59 					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
60 				bus-range = <0x00 0xff>;
63 				interrupt-map-mask = <0 0 0 7>;
64 				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
65 						<0 0 0 2 &pcie1_intc 1>,
66 						<0 0 0 3 &pcie1_intc 2>,
67 						<0 0 0 4 &pcie1_intc 3>;
69 				marvell,pcie-lane = <0>;
112 			reg = <0x10078 0x4>;
118 			reg = <0x10300 0x20>;
125 			reg = <0x11100 0x20>;
127 			#size-cells = <0>;
131 			pinctrl-0 = <&pmx_twsi1>;
138 			reg = <0x80000 0x5000>;
141 			clock-names = "0", "1";
149 			reg = <0x90000 0x200>;
152 			pinctrl-0 = <&pmx_sdio>;