Lines Matching +full:0 +full:x00002000
37 #define LGE_MODE1 0x00 /* CSR00 */
38 #define LGE_MODE2 0x04 /* CSR01 */
39 #define LGE_PPTXBUF_IDX 0x08 /* CSR02 */
40 #define LGE_PRODID 0x0C /* CSR03 */
41 #define LGE_PPTXBUF_ADDR_LO 0x10 /* CSR04 */
42 #define LGE_PPTXBUF_ADDR_HI 0x14 /* CSR05 */
43 #define LGE_RSVD0 0x18 /* CSR06 */
44 #define LGE_PPRXBUF_IDX 0x1C /* CSR07 */
45 #define LGE_PPRXBUF_ADDR_LO 0x20 /* CSR08 */
46 #define LGE_PPRXBUF_ADDR_HI 0x24 /* CSR09 */
47 #define LGE_EECTL 0x28 /* CSR10 */
48 #define LGE_CHIPSTS 0x2C /* CSR11 */
49 #define LGE_TXDESC_ADDR_LO 0x30 /* CSR12 */
50 #define LGE_TXDESC_ADDR_HI 0x34 /* CSR13 */
51 #define LGE_RXDESC_ADDR_LO 0x38 /* CSR14 */
52 #define LGE_RXDESC_ADDR_HI 0x3C /* CSR15 */
53 #define LGE_PPTXCTL 0x40 /* CSR16 */
54 #define LGE_PPRXCTL 0x44 /* CSR17 */
55 #define LGE_INTR_PERIOD 0x48 /* CSR18 */
56 #define LGE_TXFIFO_PKTCNT 0x4C /* CSR19 */
57 #define LGE_TXFIFO_LOWAT 0x50 /* CSR20 */
58 #define LGE_TXFIFO_FREEDWORDS 0x54 /* CSR21 */
59 #define LGE_TXFIFO_WRITE 0x58 /* CSR22 */
60 #define LGE_RSVD1 0x5C /* CSR23 */
61 #define LGE_RXFIFO_READ 0x60 /* CSR24 */
62 #define LGE_RSVD2 0x64 /* CSR25 */
63 #define LGE_RXFIFO_DWORDCNT 0x68 /* CSR26 */
64 #define LGE_RXFIFO_HIWAT 0x6C /* CSR27 */
65 #define LGE_RXFIFO_PKTCNT 0x70 /* CSR28 */
66 #define LGE_CMD 0x74 /* CSR29 */
67 #define LGE_IMR 0x78 /* CSR30 */
68 #define LGE_RSVD3 0x7C /* CSR31 */
69 #define LGE_ISR 0x80 /* CSR32 */
70 #define LGE_RSVD4 0x84 /* CSR33 */
71 #define LGE_MAR0 0x88 /* CSR34 */
72 #define LGE_MAR1 0x8C /* CSR35 */
73 #define LGE_LEDCFG0 0x90 /* CSR36 */
74 #define LGE_LEDCFG1 0x84 /* CSR37 */
75 #define LGE_LEDCFG2 0x98 /* CSR38 */
76 #define LGE_LEDCFG3 0x9C /* CSR39 */
77 #define LGE_RSVD5 0xA0 /* CSR40 */
78 #define LGE_EEDATA 0xA4 /* CSR41 */
79 #define LGE_PAR0 0xA8 /* CSR42 */
80 #define LGE_PAR1 0xAC /* CSR43 */
81 #define LGE_GMIICTL 0xB0 /* CSR44 */
82 #define LGE_GMIIMODE 0xB4 /* CSR45 */
83 #define LGE_STATSIDX 0xB8 /* CSR46 */
84 #define LGE_STATSVAL 0xBC /* CSR47 */
85 #define LGE_VLANCTL 0xC0 /* CSR48 */
86 #define LGE_RSVD6 0xC4 /* CSR49 */
87 #define LGE_RSVD7 0xC8 /* CSR50 */
88 #define LGE_CMDSTS 0xCC /* CSR51 */
89 #define LGE_FLOWCTL_WAT 0xD0 /* CSR52 */
90 #define LGE_RSVD8 0xD4 /* CSR53 */
91 #define LGE_RSVD9 0xD8 /* CSR54 */
92 #define LGE_RSVD10 0xDC /* CSR55 */
93 #define LGE_RSVD11 0xE0 /* CSR56 */
94 #define LGE_RSVD12 0xE4 /* CSR57 */
95 #define LGE_TIMER0_CNT 0xE8 /* CSR58 */
96 #define LGE_TIMER0_INT 0xEC /* CSR59 */
97 #define LGE_TIMER1_CNT 0xF0 /* CSR60 */
98 #define LGE_TIMER1_INT 0xF4 /* CSR61 */
99 #define LGE_DBG_CMD 0xF8 /* CSR62 */
100 #define LGE_DBG_DATA 0xFC /* CSR63 */
104 #define LGE_MODE1_SETRST_CTL0 0x00000001
105 #define LGE_MODE1_SOFTRST 0x00000002
106 #define LGE_MODE1_DEBTOD 0x00000004 /* Not documented? */
107 #define LGE_MODE1_TX_FLOWCTL 0x00000008 /* Not documented? */
108 #define LGE_MODE1_RXTXRIO 0x00000010
109 #define LGE_MODE1_GMIIPOLL 0x00000020
110 #define LGE_MODE1_TXPAD 0x00000040
111 #define LGE_MODE1_RMVPAD 0x00000080 /* Not documented? */
112 #define LGE_MODE1_SETRST_CTL1 0x00000100
113 #define LGE_MODE1_TX_ENB 0x00000200
114 #define LGE_MODE1_RX_ENB 0x00000400
115 #define LGE_MODE1_RX_MCAST 0x00000800
116 #define LGE_MODE1_RX_BCAST 0x00001000
117 #define LGE_MODE1_RX_PROMISC 0x00002000
118 #define LGE_MODE1_RX_UCAST 0x00004000
119 #define LGE_MODE1_RX_GIANTS 0x00008000
120 #define LGE_MODE1_SETRST_CTL2 0x00010000
121 #define LGE_MODE1_RX_CRC 0x00020000
122 #define LGE_MODE1_RX_ERRPKTS 0x00040000
123 #define LGE_MODE1_TX_CRC 0x00080000
124 #define LGE_MODE1_DEMDEN 0x00100000 /* Not documented? */
125 #define LGE_MODE1_MPACK_ENB 0x00200000
126 #define LGE_MODE1_MPACK_BCAST 0x00400000
127 #define LGE_MODE1_RX_FLOWCTL 0x00800000
128 #define LGE_MODE1_SETRST_CTL3 0x01000000
129 #define LGE_MODE1_VLAN_RX 0x02000000
130 #define LGE_MODE1_VLAN_TX 0x04000000
131 #define LGE_MODE1_VLAN_STRIP 0x08000000
132 #define LGE_MODE1_VLAN_INSERT 0x10000000
133 #define LGE_MODE1_GPIO_CTL0 0x20000000
134 #define LGE_MODE1_GPIO_CTL1 0x40000000
135 #define LGE_MODE1_RX_LENCHK 0x80000000
139 #define LGE_MODE2_LOOPBACK 0x000000E0
140 #define LGE_MODE2_RX_IPCSUM 0x00001000
141 #define LGE_MODE2_RX_TCPCSUM 0x00002000
142 #define LGE_MODE2_RX_UDPCSUM 0x00004000
143 #define LGE_MODE2_RX_ERRCSUM 0x00008000
147 #define LGE_EECTL_HAVE_EEPROM 0x00000001
148 #define LGE_EECTL_CMD_READ 0x00000002
149 #define LGE_EECTL_CMD_WRITE 0x00000004
150 #define LGE_EECTL_CSUMERR 0x00000010
151 #define LGE_EECTL_MULTIACCESS 0x00000020
152 #define LGE_EECTL_SINGLEACCESS 0x00000040
153 #define LGE_EECTL_ADDR 0x00001F00
154 #define LGE_EECTL_ROM_TIMING 0x000F0000
155 #define LGE_EECTL_HAVE_FLASH 0x00100000
156 #define LGE_EECTL_WRITEFLASH 0x00200000
158 #define LGE_EE_NODEADDR_0 0x12
159 #define LGE_EE_NODEADDR_1 0x13
160 #define LGE_EE_NODEADDR_2 0x10
164 #define LGE_CHIPSTS_HAVETXSPC 0x00000001 /* have room in TX FIFO for pkt */
165 #define LGE_CHIPSTS_HAVERXPKT 0x00000002 /* RX FIFO holds complete pkt */
166 #define LGE_CHIPSTS_FLOWCTL_STS 0x00000004
167 #define LGE_CHIPSTS_GPIO_STS0 0x00000008
168 #define LGE_CHIPSTS_GPIO_STS1 0x00000010
169 #define LGE_CHIPSTS_TXIDLE 0x00000020
170 #define LGE_CHIPSTS_RXIDLE 0x00000040
174 #define LGE_PPTXCTL_BUFLEN 0x0000FFFF
175 #define LGE_PPTXCTL_BUFID 0x003F0000
176 #define LGE_PPTXCTL_WANTINTR 0x01000000
180 #define LGE_PPRXCTL_BUFLEN 0x0000FFFF
181 #define LGE_PPRXCTL_BUFID 0x003F0000
182 #define LGE_PPRXCTL_WANTINTR 0x10000000
186 #define LGE_CMD_SETRST_CTL0 0x00000001
187 #define LGE_CMD_STARTTX 0x00000002
188 #define LGE_CMD_SKIP_RXPKT 0x00000004
189 #define LGE_CMD_DEL_INTREQ 0x00000008
190 #define LGE_CMD_PER_INTREQ 0x00000010
191 #define LGE_CMD_TIMER0 0x00000020
192 #define LGE_CMD_TIMER1 0x00000040
196 #define LGE_IMR_SETRST_CTL0 0x00000001
197 #define LGE_IMR_TXCMDFIFO_EMPTY 0x00000002
198 #define LGE_IMR_TXFIFO_WAT 0x00000004
199 #define LGE_IMR_TXDMA_DONE 0x00000008
200 #define LGE_IMR_DELAYEDINTR 0x00000040
201 #define LGE_IMR_INTR_ENB 0x00000080
202 #define LGE_IMR_SETRST_CTL1 0x00000100
203 #define LGE_IMR_RXCMDFIFO_EMPTY 0x00000200
204 #define LGE_IMR_RXFIFO_WAT 0x00000400
205 #define LGE_IMR_RX_DONE 0x00000800
206 #define LGE_IMR_RXDMA_DONE 0x00001000
207 #define LGE_IMR_PHY_INTR 0x00002000
208 #define LGE_IMR_MAGICPKT 0x00004000
209 #define LGE_IMR_SETRST_CTL2 0x00010000
210 #define LGE_IMR_GPIO0 0x00020000
211 #define LGE_IMR_GPIO1 0x00040000
212 #define LGE_IMR_TIMER0 0x00080000
213 #define LGE_IMR_TIMER1 0x00100000
222 #define LGE_ISR_TXCMDFIFO_EMPTY 0x00000002
223 #define LGE_ISR_TXFIFO_WAT 0x00000004
224 #define LGE_ISR_TXDMA_DONE 0x00000008
225 #define LGE_ISR_DELAYEDINTR 0x00000040
226 #define LGE_ISR_INTR_ENB 0x00000080
227 #define LGE_ISR_RXCMDFIFO_EMPTY 0x00000200
228 #define LGE_ISR_RXFIFO_WAT 0x00000400
229 #define LGE_ISR_RX_DONE 0x00000800
230 #define LGE_ISR_RXDMA_DONE 0x00001000
231 #define LGE_ISR_PHY_INTR 0x00002000
232 #define LGE_ISR_MAGICPKT 0x00004000
233 #define LGE_ISR_GPIO0 0x00020000
234 #define LGE_ISR_GPIO1 0x00040000
235 #define LGE_ISR_TIMER0 0x00080000
236 #define LGE_ISR_TIMER1 0x00100000
237 #define LGE_ISR_RXDMADONE_CNT 0xFF000000
241 #define LGE_LED0CFG_ENABLE 0x00000002
242 #define LGE_LED0CFG_INPUT_POL 0x00000004
243 #define LGE_LED0CFG_PULSE_EXP 0x00000008
244 #define LGE_LED0CFG_10MBPS 0x00000010
245 #define LGE_LED0CFG_100MBPS 0x00000100
246 #define LGE_LED0CFG_1000MBPS 0x00000200
247 #define LGE_LED0CFG_FDX 0x00000400
248 #define LGE_LED0CFG_ANEG 0x00000800
249 #define LGE_LED0CFG_LINKSTS 0x00001000
250 #define LGE_LED0CFG_RXMATCH 0x00002000
251 #define LGE_LED0CFG_TX 0x00004000
252 #define LGE_LED0CFG_RX 0x00008000
253 #define LGE_LED0CFG_JABBER 0x00010000
254 #define LGE_LED0CFG_COLLISION 0x00020000
255 #define LGE_LED0CFG_CARRIER 0x00040000
256 #define LGE_LED0CFG_LEDOUT 0x10000000
260 #define LGE_LED1CFG_ENABLE 0x00000002
261 #define LGE_LED1CFG_INPUT_POL 0x00000004
262 #define LGE_LED1CFG_PULSE_EXP 0x00000008
263 #define LGE_LED1CFG_10MBPS 0x00000010
264 #define LGE_LED1CFG_100MBPS 0x00000100
265 #define LGE_LED1CFG_1000MBPS 0x00000200
266 #define LGE_LED1CFG_FDX 0x00000400
267 #define LGE_LED1CFG_ANEG 0x00000800
268 #define LGE_LED1CFG_LINKSTS 0x00001000
269 #define LGE_LED1CFG_RXMATCH 0x00002000
270 #define LGE_LED1CFG_TX 0x00004000
271 #define LGE_LED1CFG_RX 0x00008000
272 #define LGE_LED1CFG_JABBER 0x00010000
273 #define LGE_LED1CFG_COLLISION 0x00020000
274 #define LGE_LED1CFG_CARRIER 0x00040000
275 #define LGE_LED1CFG_LEDOUT 0x10000000
279 #define LGE_LED2CFG_ENABLE 0x00000002
280 #define LGE_LED2CFG_INPUT_POL 0x00000004
281 #define LGE_LED2CFG_PULSE_EXP 0x00000008
282 #define LGE_LED2CFG_10MBPS 0x00000010
283 #define LGE_LED2CFG_100MBPS 0x00000100
284 #define LGE_LED2CFG_1000MBPS 0x00000200
285 #define LGE_LED2CFG_FDX 0x00000400
286 #define LGE_LED2CFG_ANEG 0x00000800
287 #define LGE_LED2CFG_LINKSTS 0x00001000
288 #define LGE_LED2CFG_RXMATCH 0x00002000
289 #define LGE_LED2CFG_TX 0x00004000
290 #define LGE_LED2CFG_RX 0x00008000
291 #define LGE_LED2CFG_JABBER 0x00010000
292 #define LGE_LED2CFG_COLLISION 0x00020000
293 #define LGE_LED2CFG_CARRIER 0x00040000
294 #define LGE_LED2CFG_LEDOUT 0x10000000
298 #define LGE_GMIICTL_PHYREG 0x0000001F
299 #define LGE_GMIICTL_CMD 0x00000080
300 #define LGE_GMIICTL_PHYADDR 0x00001F00
301 #define LGE_GMIICTL_CMDBUSY 0x00008000
302 #define LGE_GMIICTL_DATA 0xFFFF0000
304 #define LGE_GMIICMD_READ 0x00000000
305 #define LGE_GMIICMD_WRITE 0x00000080
308 #define LGE_GMIIMODE_SPEED 0x00000003
309 #define LGE_GMIIMODE_FDX 0x00000004
310 #define LGE_GMIIMODE_PROTSEL 0x00000100 /* 0 == GMII, 1 == TBI */
311 #define LGE_GMIIMODE_PCSENH 0x00000200
313 #define LGE_SPEED_10 0x00000000
314 #define LGE_SPEED_100 0x00000001
315 #define LGE_SPEED_1000 0x00000002
319 #define LGE_VLANCTL_VLID 0x00000FFF
320 #define LGE_VLANCTL_USERPRIO 0x0000E000
321 #define LGE_VLANCTL_TCI_IDX 0x000D0000
322 #define LGE_VLANCTL_TBLCMD 0x00200000
326 #define LGE_CMDSTS_TXDMADONE 0x000000FF
327 #define LGE_CMDSTS_RXDMADONE 0x0000FF00
328 #define LGE_CMDSTS_TXCMDFREE 0x003F0000
329 #define LGE_CMDSTS_RXCMDFREE 0x3F000000
339 #define LGE_STATS_TX_PKTS_OK 0x00
340 #define LGE_STATS_SINGLE_COLL_PKTS 0x01
341 #define LGE_STATS_MULTI_COLL_PKTS 0x02
342 #define LGE_STATS_RX_PKTS_OK 0x03
343 #define LGE_STATS_FCS_ERRS 0x04
344 #define LGE_STATS_ALIGN_ERRS 0x05
345 #define LGE_STATS_DROPPED_PKTS 0x06
346 #define LGE_STATS_RX_ERR_PKTS 0x07
347 #define LGE_STATS_TX_ERR_PKTS 0x08
348 #define LGE_STATS_LATE_COLLS 0x09
349 #define LGE_STATS_RX_RUNTS 0x0A
350 #define LGE_STATS_RX_GIANTS 0x0B
351 #define LGE_STATS_VLAN_PKTS_ACCEPT 0x0C
352 #define LGE_STATS_VLAN_PKTS_REJECT 0x0D
353 #define LGE_STATS_IP_CSUM_ERR 0x0E
354 #define LGE_STATS_UDP_CSUM_ERR 0x0F
355 #define LGE_STATS_RANGELEN_ERRS 0x10
356 #define LGE_STATS_TCP_CSUM_ERR 0x11
357 #define LGE_STATS_RSVD0 0x12
358 #define LGE_STATS_TX_EXCESS_COLLS 0x13
359 #define LGE_STATS_RX_UCASTS 0x14
360 #define LGE_STATS_RX_MCASTS 0x15
361 #define LGE_STATS_RX_BCASTS 0x16
362 #define LGE_STATS_RX_PAUSE_PKTS 0x17
363 #define LGE_STATS_TX_PAUSE_PKTS 0x18
364 #define LGE_STATS_TX_PKTS_DEFERRED 0x19
365 #define LGE_STATS_TX_EXCESS_DEFER 0x1A
366 #define LGE_STATS_CARRIER_SENSE_ERR 0x1B
415 #define LGE_RXCTL_BUFLEN 0x0000FFFF
416 #define LGE_RXCTL_FRAGCNT 0x001F0000
417 #define LGE_RXCTL_LENERR 0x00400000
418 #define LGE_RXCTL_UCAST 0x00800000
419 #define LGR_RXCTL_BCAST 0x01000000
420 #define LGE_RXCTL_MCAST 0x02000000
421 #define LGE_RXCTL_GIANT 0x04000000
422 #define LGE_RXCTL_OFLOW 0x08000000
423 #define LGE_RXCTL_CRCERR 0x10000000
424 #define LGE_RXCTL_RUNT 0x20000000
425 #define LGE_RXCTL_ALGNERR 0x40000000
426 #define LGE_RXCTL_WANTINTR 0x80000000
433 #define LGE_RXSTS_VLTBIDX 0x0000000F
434 #define LGE_RXSTS_VLTBLHIT 0x00000010
435 #define LGE_RXSTS_IPCSUMERR 0x00000100
436 #define LGE_RXSTS_TCPCSUMERR 0x00000200
437 #define LGE_RXSTS_UDPCSUMERR 0x00000400
438 #define LGE_RXSTS_ISIP 0x00000800
439 #define LGE_RXSTS_ISTCP 0x00001000
440 #define LGE_RXSTS_ISUDP 0x00002000
442 #define LGE_TXCTL_BUFLEN 0x0000FFFF
443 #define LGE_TXCTL_FRAGCNT 0x001F0000
444 #define LGE_TXCTL_VLTBIDX 0x0F000000
445 #define LGE_TXCTL_VLIS 0x10000000
446 #define LGE_TXCTL_WANTINTR 0x80000000
452 #define LGE_RXBYTES(x) (x->lge_ctl & 0xFFFF)
468 #define LGE_VENDORID 0x1394
473 #define LGE_DEVICEID 0x0001
563 #define LGE_PCI_VENDOR_ID 0x00
564 #define LGE_PCI_DEVICE_ID 0x02
565 #define LGE_PCI_COMMAND 0x04
566 #define LGE_PCI_STATUS 0x06
567 #define LGE_PCI_REVID 0x08
568 #define LGE_PCI_CLASSCODE 0x09
569 #define LGE_PCI_CACHELEN 0x0C
570 #define LGE_PCI_LATENCY_TIMER 0x0D
571 #define LGE_PCI_HEADER_TYPE 0x0E
572 #define LGE_PCI_LOIO 0x10
573 #define LGE_PCI_LOMEM 0x14
574 #define LGE_PCI_BIOSROM 0x30
575 #define LGE_PCI_INTLINE 0x3C
576 #define LGE_PCI_INTPIN 0x3D
577 #define LGE_PCI_MINGNT 0x3E
578 #define LGE_PCI_MINLAT 0x0F
579 #define LGE_PCI_RESETOPT 0x48
580 #define LGE_PCI_EEPROM_DATA 0x4C
583 #define LGE_PCI_CAPID 0x50 /* 8 bits */
584 #define LGE_PCI_NEXTPTR 0x51 /* 8 bits */
585 #define LGE_PCI_PWRMGMTCAP 0x52 /* 16 bits */
586 #define LGE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
588 #define LGE_PSTATE_MASK 0x0003
589 #define LGE_PSTATE_D0 0x0000
590 #define LGE_PSTATE_D1 0x0001
591 #define LGE_PSTATE_D2 0x0002
592 #define LGE_PSTATE_D3 0x0003
593 #define LGE_PME_EN 0x0010
594 #define LGE_PME_STATUS 0x8000