Lines Matching +full:0 +full:x00002000
27 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
34 clocks = <&cpuclk 0>;
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
69 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
70 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
71 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
72 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
73 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
74 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
75 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
76 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
77 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
78 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
79 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
80 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
81 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
83 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
84 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
85 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
86 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
87 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
88 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
89 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
90 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
92 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
93 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
95 pcie1: pcie@1,0 {
97 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
98 reg = <0x0800 0 0 0 0>;
104 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
105 0x81000000 0 0 0x81000000 0x1 0 1 0>;
106 bus-range = <0x00 0xff>;
107 interrupt-map-mask = <0 0 0 7>;
108 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
109 <0 0 0 2 &pcie1_intc 1>,
110 <0 0 0 3 &pcie1_intc 2>,
111 <0 0 0 4 &pcie1_intc 3>;
112 marvell,pcie-port = <0>;
113 marvell,pcie-lane = <0>;
123 pcie2: pcie@2,0 {
125 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
126 reg = <0x1000 0 0 0 0>;
132 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
133 0x81000000 0 0 0x81000000 0x2 0 1 0>;
134 bus-range = <0x00 0xff>;
135 interrupt-map-mask = <0 0 0 7>;
136 interrupt-map = <0 0 0 1 &pcie2_intc 0>,
137 <0 0 0 2 &pcie2_intc 1>,
138 <0 0 0 3 &pcie2_intc 2>,
139 <0 0 0 4 &pcie2_intc 3>;
140 marvell,pcie-port = <0>;
151 pcie3: pcie@3,0 {
153 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
154 reg = <0x1800 0 0 0 0>;
160 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
161 0x81000000 0 0 0x81000000 0x3 0 1 0>;
162 bus-range = <0x00 0xff>;
163 interrupt-map-mask = <0 0 0 7>;
164 interrupt-map = <0 0 0 1 &pcie3_intc 0>,
165 <0 0 0 2 &pcie3_intc 1>,
166 <0 0 0 3 &pcie3_intc 2>,
167 <0 0 0 4 &pcie3_intc 3>;
168 marvell,pcie-port = <0>;
179 pcie4: pcie@4,0 {
181 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
182 reg = <0x2000 0 0 0 0>;
188 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
189 0x81000000 0 0 0x81000000 0x4 0 1 0>;
190 bus-range = <0x00 0xff>;
191 interrupt-map-mask = <0 0 0 7>;
192 interrupt-map = <0 0 0 1 &pcie4_intc 0>,
193 <0 0 0 2 &pcie4_intc 1>,
194 <0 0 0 3 &pcie4_intc 2>,
195 <0 0 0 4 &pcie4_intc 3>;
196 marvell,pcie-port = <0>;
207 pcie5: pcie@5,0 {
209 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
210 reg = <0x2800 0 0 0 0>;
216 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
217 0x81000000 0 0 0x81000000 0x5 0 1 0>;
218 bus-range = <0x00 0xff>;
219 interrupt-map-mask = <0 0 0 7>;
220 interrupt-map = <0 0 0 1 &pcie5_intc 0>,
221 <0 0 0 2 &pcie5_intc 1>,
222 <0 0 0 3 &pcie5_intc 2>,
223 <0 0 0 4 &pcie5_intc 3>;
225 marvell,pcie-lane = <0>;
235 pcie6: pcie@6,0 {
237 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
238 reg = <0x3000 0 0 0 0>;
244 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
245 0x81000000 0 0 0x81000000 0x6 0 1 0>;
246 bus-range = <0x00 0xff>;
247 interrupt-map-mask = <0 0 0 7>;
248 interrupt-map = <0 0 0 1 &pcie6_intc 0>,
249 <0 0 0 2 &pcie6_intc 1>,
250 <0 0 0 3 &pcie6_intc 2>,
251 <0 0 0 4 &pcie6_intc 3>;
263 pcie7: pcie@7,0 {
265 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
266 reg = <0x3800 0 0 0 0>;
272 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
273 0x81000000 0 0 0x81000000 0x7 0 1 0>;
274 bus-range = <0x00 0xff>;
275 interrupt-map-mask = <0 0 0 7>;
276 interrupt-map = <0 0 0 1 &pcie7_intc 0>,
277 <0 0 0 2 &pcie7_intc 1>,
278 <0 0 0 3 &pcie7_intc 2>,
279 <0 0 0 4 &pcie7_intc 3>;
291 pcie8: pcie@8,0 {
293 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
294 reg = <0x4000 0 0 0 0>;
300 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
301 0x81000000 0 0 0x81000000 0x8 0 1 0>;
302 bus-range = <0x00 0xff>;
303 interrupt-map-mask = <0 0 0 7>;
304 interrupt-map = <0 0 0 1 &pcie8_intc 0>,
305 <0 0 0 2 &pcie8_intc 1>,
306 <0 0 0 3 &pcie8_intc 2>,
307 <0 0 0 4 &pcie8_intc 3>;
319 pcie9: pcie@9,0 {
321 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
322 reg = <0x4800 0 0 0 0>;
328 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
329 0x81000000 0 0 0x81000000 0x9 0 1 0>;
330 bus-range = <0x00 0xff>;
331 interrupt-map-mask = <0 0 0 7>;
332 interrupt-map = <0 0 0 1 &pcie9_intc 0>,
333 <0 0 0 2 &pcie9_intc 1>,
334 <0 0 0 3 &pcie9_intc 2>,
335 <0 0 0 4 &pcie9_intc 3>;
337 marvell,pcie-lane = <0>;
352 reg = <0x18100 0x40>, <0x181c0 0x08>;
361 clocks = <&coreclk 0>;
367 reg = <0x18140 0x40>, <0x181c8 0x08>;
376 clocks = <&coreclk 0>;
382 reg = <0x18180 0x40>;
393 reg = <0x34000 0x4000>;