Lines Matching +full:0 +full:x00002000
28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
66 * MV78460 has 4 PCIe units Gen2.0: Two units can be
79 bus-range = <0x00 0xff>;
82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
86 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
87 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
88 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
89 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
90 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
91 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
92 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
93 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
94 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
95 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
96 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
97 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
98 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
99 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
101 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
102 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
103 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
104 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
105 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
106 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
107 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
108 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
110 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
111 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
113 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
114 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
116 pcie1: pcie@1,0 {
118 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
119 reg = <0x0800 0 0 0 0>;
125 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
126 0x81000000 0 0 0x81000000 0x1 0 1 0>;
127 bus-range = <0x00 0xff>;
128 interrupt-map-mask = <0 0 0 7>;
129 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
130 <0 0 0 2 &pcie1_intc 1>,
131 <0 0 0 3 &pcie1_intc 2>,
132 <0 0 0 4 &pcie1_intc 3>;
133 marvell,pcie-port = <0>;
134 marvell,pcie-lane = <0>;
144 pcie2: pcie@2,0 {
146 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
147 reg = <0x1000 0 0 0 0>;
153 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
154 0x81000000 0 0 0x81000000 0x2 0 1 0>;
155 bus-range = <0x00 0xff>;
156 interrupt-map-mask = <0 0 0 7>;
157 interrupt-map = <0 0 0 1 &pcie2_intc 0>,
158 <0 0 0 2 &pcie2_intc 1>,
159 <0 0 0 3 &pcie2_intc 2>,
160 <0 0 0 4 &pcie2_intc 3>;
161 marvell,pcie-port = <0>;
172 pcie3: pcie@3,0 {
174 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
175 reg = <0x1800 0 0 0 0>;
181 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
182 0x81000000 0 0 0x81000000 0x3 0 1 0>;
183 bus-range = <0x00 0xff>;
184 interrupt-map-mask = <0 0 0 7>;
185 interrupt-map = <0 0 0 1 &pcie3_intc 0>,
186 <0 0 0 2 &pcie3_intc 1>,
187 <0 0 0 3 &pcie3_intc 2>,
188 <0 0 0 4 &pcie3_intc 3>;
189 marvell,pcie-port = <0>;
200 pcie4: pcie@4,0 {
202 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
203 reg = <0x2000 0 0 0 0>;
209 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
210 0x81000000 0 0 0x81000000 0x4 0 1 0>;
211 bus-range = <0x00 0xff>;
212 interrupt-map-mask = <0 0 0 7>;
213 interrupt-map = <0 0 0 1 &pcie4_intc 0>,
214 <0 0 0 2 &pcie4_intc 1>,
215 <0 0 0 3 &pcie4_intc 2>,
216 <0 0 0 4 &pcie4_intc 3>;
217 marvell,pcie-port = <0>;
228 pcie5: pcie@5,0 {
230 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
231 reg = <0x2800 0 0 0 0>;
237 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
238 0x81000000 0 0 0x81000000 0x5 0 1 0>;
239 bus-range = <0x00 0xff>;
240 interrupt-map-mask = <0 0 0 7>;
241 interrupt-map = <0 0 0 1 &pcie5_intc 0>,
242 <0 0 0 2 &pcie5_intc 1>,
243 <0 0 0 3 &pcie5_intc 2>,
244 <0 0 0 4 &pcie5_intc 3>;
246 marvell,pcie-lane = <0>;
256 pcie6: pcie@6,0 {
258 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
259 reg = <0x3000 0 0 0 0>;
265 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
266 0x81000000 0 0 0x81000000 0x6 0 1 0>;
267 bus-range = <0x00 0xff>;
268 interrupt-map-mask = <0 0 0 7>;
269 interrupt-map = <0 0 0 1 &pcie6_intc 0>,
270 <0 0 0 2 &pcie6_intc 1>,
271 <0 0 0 3 &pcie6_intc 2>,
272 <0 0 0 4 &pcie6_intc 3>;
284 pcie7: pcie@7,0 {
286 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
287 reg = <0x3800 0 0 0 0>;
293 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
294 0x81000000 0 0 0x81000000 0x7 0 1 0>;
295 bus-range = <0x00 0xff>;
296 interrupt-map-mask = <0 0 0 7>;
297 interrupt-map = <0 0 0 1 &pcie7_intc 0>,
298 <0 0 0 2 &pcie7_intc 1>,
299 <0 0 0 3 &pcie7_intc 2>,
300 <0 0 0 4 &pcie7_intc 3>;
312 pcie8: pcie@8,0 {
314 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
315 reg = <0x4000 0 0 0 0>;
321 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
322 0x81000000 0 0 0x81000000 0x8 0 1 0>;
323 bus-range = <0x00 0xff>;
324 interrupt-map-mask = <0 0 0 7>;
325 interrupt-map = <0 0 0 1 &pcie8_intc 0>,
326 <0 0 0 2 &pcie8_intc 1>,
327 <0 0 0 3 &pcie8_intc 2>,
328 <0 0 0 4 &pcie8_intc 3>;
340 pcie9: pcie@9,0 {
342 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
343 reg = <0x4800 0 0 0 0>;
349 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
350 0x81000000 0 0 0x81000000 0x9 0 1 0>;
351 bus-range = <0x00 0xff>;
352 interrupt-map-mask = <0 0 0 7>;
353 interrupt-map = <0 0 0 1 &pcie9_intc 0>,
354 <0 0 0 2 &pcie9_intc 1>,
355 <0 0 0 3 &pcie9_intc 2>,
356 <0 0 0 4 &pcie9_intc 3>;
358 marvell,pcie-lane = <0>;
368 pcie10: pcie@a,0 {
370 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
371 reg = <0x5000 0 0 0 0>;
377 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
378 0x81000000 0 0 0x81000000 0xa 0 1 0>;
379 bus-range = <0x00 0xff>;
380 interrupt-map-mask = <0 0 0 7>;
381 interrupt-map = <0 0 0 1 &pcie10_intc 0>,
382 <0 0 0 2 &pcie10_intc 1>,
383 <0 0 0 3 &pcie10_intc 2>,
384 <0 0 0 4 &pcie10_intc 3>;
386 marvell,pcie-lane = <0>;
401 reg = <0x18100 0x40>, <0x181c0 0x08>;
410 clocks = <&coreclk 0>;
416 reg = <0x18140 0x40>, <0x181c8 0x08>;
425 clocks = <&coreclk 0>;
431 reg = <0x18180 0x40>;
442 reg = <0x34000 0x4000>;