Lines Matching +full:0 +full:x00002000
16 cpu0: cpu@0 {
19 reg = <0x0>;
20 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
29 reg = <0x1>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
39 reg = <0x100>;
49 reg = <0x101>;
59 reg = <0x200>;
69 reg = <0x201>;
79 reg = <0x300>;
89 reg = <0x301>;
123 arm,psci-suspend-param = <0x00010000>;
131 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
132 <0x10 0x00000000 0x0 0x00002000>; /* configuration space */
134 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
135 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
139 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
140 <0x12 0x00000000 0x0 0x00002000>; /* configuration space */
142 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
143 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
147 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
148 <0x14 0x00000000 0x0 0x00002000>; /* configuration space */
150 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
151 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
155 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
156 <0x16 0x00000000 0x0 0x00002000>; /* configuration space */
158 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
159 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */