| /freebsd/sys/contrib/device-tree/Bindings/hwmon/ |
| H A D | max6697.txt | 4 - compatible:
16 - reg: I2C address
20 - smbus-timeout-disable
23 - extended-range-enable
24 Only valid for MAX6581. Set to enable extended temperature range.
26 - beta-compensation-enable
27 Only valid for MAX6693 and MX6694. Set to enable beta compensation on
30 - alert-mask
31 Alert bit mask. Alert disabled for bits set.
34 - over-temperature-mask
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| /freebsd/sys/contrib/device-tree/src/arm64/hisilicon/ |
| H A D | poplar-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016-2018 HiSilicon Technologies Co., Ltd.
8 #include <dt-bindings/pinctrl/hisi.h>
10 /* value, enable bits, disable bits, mask */
11 #define PINCTRL_PULLDOWN(value, enable, disable, mask) \ argument
12 (value << 13) (enable << 13) (disable << 13) (mask << 13)
13 #define PINCTRL_PULLUP(value, enable, disable, mask) \ argument
14 (value << 12) (enable << 12) (disable << 12) (mask << 12)
15 #define PINCTRL_SLEW_RATE(value, mask) (value << 8) (mask << 8) argument
16 #define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4) argument
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| /freebsd/sys/dev/ath/ath_hal/ar5211/ |
| H A D | ar5211reg.h | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2006 Atheros Communications, Inc.
35 #define AR_IER 0x0024 /* Interrupt enable register */
55 #define AR_IMR 0x00a0 /* Primary interrupt mask register */
56 #define AR_IMR_S0 0x00a4 /* Secondary interrupt mask reg 0 */
57 #define AR_IMR_S1 0x00a8 /* Secondary interrupt mask reg 1 */
58 #define AR_IMR_S2 0x00ac /* Secondary interrupt mask reg 2 */
59 #define AR_IMR_S3 0x00b0 /* Secondary interrupt mask reg 3 */
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| /freebsd/sys/contrib/alpine-hal/eth/ |
| H A D | al_hal_eth_ec_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
62 /* [0x4] Enable modules operation. */
64 /* [0x8] Enable FIFO operation on the EC side. */
72 /* [0x18] Enable modules operation (extended operations). */
175 /* [0x4] Mask for comparison */
214 /* [0x38] VLAN p-bits table address */
216 /* [0x3c] VLAN p-bits table data */
280 /* [0xb8] Tuple (4/2) Hash configuration , mask for the input ... */
282 /* [0xbc] Tuple (4/2) Hash configuration , mask for the input ... */
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| /freebsd/sys/contrib/device-tree/Bindings/regulator/ |
| H A D | ti-abb-regulator.txt | 4 - compatible: Should be one of:
5 - "ti,abb-v1" for older SoCs like OMAP3
6 - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
7 - "ti,abb-v3" for a generic definition where setup and control registers are
9 - reg: Address and length of the register set for the device. It contains
10 the information of registers in the same order as described by reg-names
11 - reg-names: Should contain the reg names
12 - "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2)
13 - "control-address" - contains control register address of ABB module (ti,abb-v3)
14 - "setup-address" - contains setup register address of ABB module (ti,abb-v3)
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| /freebsd/sys/dev/ath/ath_hal/ar5212/ |
| H A D | ar5212reg.h | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
30 #define AR_IER 0x0024 /* MAC Interrupt enable register */
52 #define AR_IMR 0x00a0 /* MAC Primary interrupt mask register */
53 #define AR_IMR_S0 0x00a4 /* MAC Secondary interrupt mask register 0 */
54 #define AR_IMR_S1 0x00a8 /* MAC Secondary interrupt mask register 1 */
55 #define AR_IMR_S2 0x00ac /* MAC Secondary interrupt mask register 2 */
56 #define AR_IMR_S3 0x00b0 /* MAC Secondary interrupt mask register 3 */
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| /freebsd/sys/contrib/device-tree/src/arm64/apm/ |
| H A D | apm-storm.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | pinctrl-single.txt | 1 One-register-per-pin type device tree based pinctrl driver
4 - compatible : "pinctrl-single" or "pinconf-single".
5 "pinctrl-single" means that pinconf isn't supported.
6 "pinconf-single" means that generic pinconf is supported.
8 - reg : offset and length of the register set for the mux registers
10 - #pinctrl-cells : number of cells in addition to the index, set to 1
11 or 2 for pinctrl-single,pins and set to 2 for pinctrl-single,bits
13 - pinctrl-single,register-width : pinmux register access width in bits
15 - pinctrl-single,function-mask : mask of allowed pinmux function bits
19 - pinctrl-single,function-off : function off mode for disabled state if
[all …]
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| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300reg.h | 32 /* MAC Control Register - only write values of 1 have effect */
34 #define AR_CR_LP_RXE 0x00000004 // Receive LPQ enable
35 #define AR_CR_HP_RXE 0x00000008 // Receive HPQ enable
37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt
47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
51 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 // Mask of PCI core master request queue…
55 /* Rx DMA Data Buffer Pointer Threshold - High and Low Priority register */
70 /* MAC Global Interrupt enable register */
72 #define AR_IER_ENABLE 0x00000001 // Global interrupt enable
109 #define AR_FTRIG 0x000003F0 // Mask for Frame trigger level
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| /freebsd/sys/dev/bfe/ |
| H A D | if_bfereg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 #define BFE_PFE 0x00000080 /* Pattern Filtering Enable */
41 #define BFE_PME 0x00001000 /* PHY Mode Enable */
42 #define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */
46 #define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */
66 #define BFE_IMASK 0x00000024 /* Interrupt Mask */
71 #define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */
79 #define BFE_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */
87 #define BFE_TX_CTRL_ENABLE 0x00000001 /* Enable */
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| /freebsd/usr.sbin/binmiscctl/ |
| H A D | binmiscctl.8 | 1 .\"-
38 .Fl -interpreter
40 .Fl -magic
42 .Fl -size
44 .Op Fl -mask Ar mask
45 .Op Fl -offset Ar offset
46 .Op Fl -set-enabled
47 .Op Fl -pre-open
52 .Cm enable
76 .Bl -tag -width indent
[all …]
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| /freebsd/sys/arm64/rockchip/ |
| H A D | rk3399_emmcphy.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
102 { "rockchip,rk3399-emmc-phy", 1 },
112 #define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask)) argument
113 #define SHIFTIN(x, mask) ((x) * LOWEST_SET_BIT(mask)) argument
116 static int rk_emmcphy_enable(struct phynode *phynode, bool enable);
126 rk_emmcphy_enable(struct phynode *phynode, bool enable) in rk_emmcphy_enable() argument
132 uint32_t mask, val; in rk_emmcphy_enable() local
146 if (enable) { in rk_emmcphy_enable()
148 mask = PHYCTRL_DR_TY; in rk_emmcphy_enable()
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | st,spear-spics-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/st,spear-spics-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <vireshk@kernel.org>
27 const: st,spear-spics-gpio
32 gpio-controller: true
34 '#gpio-cells':
37 st-spics,peripcfg-reg:
41 st-spics,sw-enable-bit:
[all …]
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| H A D | spear_spics.txt | 17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
25 * #gpio-cells: should be 1 and will mention chip select number
30 -------
32 compatible = "st,spear-spics-gpio";
[all …]
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| /freebsd/sys/dev/msk/ |
| H A D | if_mskreg.h | 17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | xgene.txt | 1 Device Tree Clock bindings for APM X-Gene
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
17 - reg : shall be the physical PLL register address for the pll clock.
[all …]
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| H A D | apm,xgene-device-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: APM X-Gene SoC device clocks
10 - Khuong Dinh <khuong@os.amperecomputing.com>
14 const: apm,xgene-device-clock
20 reg-names:
22 - enum: [ csr-reg, div-reg ]
23 - const: div-reg
[all …]
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| H A D | vt8500.txt | 1 Device Tree Clock bindings for arch-vt8500
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
13 "via,vt8500-device-clock" - for a VT/WM device clock
16 - reg : shall be the control register offset from PMC base for the pll clock.
17 - clocks : shall be the input parent clock phandle for the clock. This should
[all …]
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| /freebsd/sys/contrib/ncsw/Peripherals/FM/ |
| H A D | fman_ncsw.c | 2 * Copyright 2008-2012 Freescale Semiconductor Inc.
40 uint32_t event, mask, force; in fman_get_bmi_err_event() local
42 event = ioread32be(&bmi_rg->fmbm_ievr); in fman_get_bmi_err_event()
43 mask = ioread32be(&bmi_rg->fmbm_ier); in fman_get_bmi_err_event()
44 event &= mask; in fman_get_bmi_err_event()
46 force = ioread32be(&bmi_rg->fmbm_ifr); in fman_get_bmi_err_event()
48 iowrite32be(force & ~event, &bmi_rg->fmbm_ifr); in fman_get_bmi_err_event()
50 iowrite32be(event, &bmi_rg->fmbm_ievr); in fman_get_bmi_err_event()
56 uint32_t event, mask, force; in fman_get_qmi_err_event() local
58 event = ioread32be(&qmi_rg->fmqm_eie); in fman_get_qmi_err_event()
[all …]
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| /freebsd/sys/dev/ic/ |
| H A D | cd180.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
51 #define CD180_IER 0x02 /* Interrupt Enable Register */
80 #define GICR_CHAN 0x1C /* Channel Number Mask */
84 #define CAR_CHAN 0x07 /* Channel Number Mask */
93 #define RCSR_SCMASK 0x70 /* Special Character Detected Mask */
110 #define CCR_RCVREN 0x12 /* Receiver Enable */
112 #define CCR_XMTREN 0x18 /* Transmitter Enable */
114 /* Interrupt Enable Register */
115 #define IER_DSR 0x80 /* Enable interrupt on DSR change */
[all …]
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| /freebsd/sys/dev/igc/ |
| H A D | igc_defines.h | 1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
16 #define IGC_WUC_APME 0x00000001 /* APM Enable */
17 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
23 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
24 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
25 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
26 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
27 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
28 #define IGC_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
[all …]
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| /freebsd/sys/dev/e1000/ |
| H A D | e1000_defines.h | 2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
44 #define E1000_WUC_APME 0x00000001 /* APM Enable */
45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
51 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
54 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
55 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
56 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
[all …]
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| /freebsd/sys/dev/qat/qat_hw/qat_200xx/ |
| H A D | adf_200xx_hw_data.c | 1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
30 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_accel_mask()
45 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_ae_mask()
73 if (!self || !self->accel_mask) in get_num_accels()
77 if (self->accel_mask & (1 << i)) in get_num_accels()
88 if (!self || !self->ae_mask) in get_num_aes()
92 if (self->ae_mask & (1 << i)) in get_num_aes()
132 struct adf_hw_device_data *hw_device = accel_dev->hw_device; in adf_get_arbiter_mapping()
136 if (hw_device->ae_mask & (1 << i)) in adf_get_arbiter_mapping()
[all …]
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| /freebsd/sys/dev/rtwn/rtl8821a/ |
| H A D | r21a_init.c | 1 /*-
78 /* Enable WL suspend. */ in r21a_power_on()
82 /* Enable LDOA12 MACRO block for all interfaces. */ in r21a_power_on()
108 device_printf(sc->sc_dev, in r21a_power_on()
144 /* Enable falling edge triggering interrupt. */ in r21a_power_on()
147 /* Enable GPIO9 interrupt mode. */ in r21a_power_on()
150 /* Enable GPIO9 input mode. */ in r21a_power_on()
153 /* Enable HSISR GPIO interrupt. */ in r21a_power_on()
156 /* Enable HSISR GPIO9 interrupt. */ in r21a_power_on()
164 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ in r21a_power_on()
[all …]
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| /freebsd/sys/dev/aic7xxx/ |
| H A D | aic7xxx.reg | 1 /*-
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
19 * 3. Neither the names of the above-listed copyright holders nor the names
47 * All page numbers refer to the Adaptec AIC-7770 Data Book available from
48 * Adaptec's Technical Documents Department 1-800-934-2766
52 * SCSI Sequence Control (p. 3-11).
69 * SCSI Transfer Control 0 Register (pp. 3-13).
85 * SCSI Transfer Control 1 Register (pp. 3-14,15).
94 mask STIMESEL 0x18
[all …]
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