Lines Matching +full:enable +full:- +full:mask
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 #define BFE_PFE 0x00000080 /* Pattern Filtering Enable */
41 #define BFE_PME 0x00001000 /* PHY Mode Enable */
42 #define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */
46 #define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */
66 #define BFE_IMASK 0x00000024 /* Interrupt Mask */
71 #define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */
79 #define BFE_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */
87 #define BFE_TX_CTRL_ENABLE 0x00000001 /* Enable */
89 #define BFE_TX_CTRL_LPBACK 0x00000004 /* Loopback Enable */
96 #define BFE_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */
97 #define BFE_STAT_SMASK 0x0000f000 /* State Mask */
103 #define BFE_STAT_EMASK 0x000f0000 /* Error Mask */
112 #define BFE_RX_CTRL_ENABLE 0x00000001 /* Enable */
113 #define BFE_RX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */
124 #define BFE_RXCONF_PROMISC 0x00000008 /* Promiscuous Enable */
125 #define BFE_RXCONF_LPBACK 0x00000010 /* Loopback Enable */
126 #define BFE_RXCONF_FLOW 0x00000020 /* Flow Control Enable */
135 #define BFE_MDIO_PREAMBLE 0x00000080 /* MII Preamble Enable */
155 #define BFE_EMAC_IMASK 0x00000418 /* EMAC Interrupt Mask */
166 #define BFE_CAM_ENABLE 0x00000001 /* CAM Enable */
167 #define BFE_CAM_MSEL 0x00000002 /* Mask Select */
170 #define BFE_CAM_INDEX_MASK 0x003f0000 /* Index Mask */
175 #define BFE_ENET_ENABLE 0x00000001 /* EMAC Enable */
183 #define BFE_TX_SBENAB 0x00000004 /* Single Backoff Enable */
238 #define BFE_RX_NPAUSE 0x000005D8 /* MIB RX Non-Pause Packets */
253 #define BFE_SBINTVEC 0x00000F94 /* BFE_SB Interrupt Mask */
254 #define BFE_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
255 #define BFE_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
256 #define BFE_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */
257 #define BFE_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */
258 #define BFE_INTVEC_USB 0x00000010 /* Enable interrupts for usb */
259 #define BFE_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */
260 #define BFE_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
265 #define BFE_CLOCK 0x00010000 /* Clock Enable */
267 #define BFE_PE 0x40000000 /* Power Management Enable */
268 #define BFE_BE 0x80000000 /* BIST Enable */
271 #define BFE_SERR 0x00000001 /* S-error */
299 #define BFE_LOW_CD_MASK 0x000000ff /* Clock Divide Mask */
300 #define BFE_LOW_CO_MASK 0x0000f800 /* Clock Offset Mask */
301 #define BFE_LOW_IF_MASK 0x00fc0000 /* Interrupt Flags Mask */
302 #define BFE_LOW_IM_MASK 0x03000000 /* Interrupt Mode Mask */
333 #define BFE_CS_MASK 0x00000003 /* Config Space Mask */
444 #define CSR_READ_4(sc, reg) bus_read_4(sc->bfe_res, reg)
446 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->bfe_res, reg, val)
454 #define BFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bfe_mtx, MA_OWNED)
455 #define BFE_LOCK(_sc) mtx_lock(&(_sc)->bfe_mtx)
456 #define BFE_UNLOCK(_sc) mtx_unlock(&(_sc)->bfe_mtx)
458 #define BFE_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1
530 #define BFE_MIB_CNT (MIB_RX_NPAUSE - MIB_TX_GOOD_O + 1)