Lines Matching +full:enable +full:- +full:mask
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
44 #define E1000_WUC_APME 0x00000001 /* APM Enable */
45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
51 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
54 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
55 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
56 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
57 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
58 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
80 #define E1000_CTRL_EXT_SDLPE 0X00040000 /* SerDes Low Power Enable */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
144 /* mask to determine if packets should be dropped due to frame errors */
152 /* Same mask, but for extended and packet split descriptors */
172 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
173 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
174 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
177 /* Enable MAC address filtering */
179 /* Enable MNG packets to host memory */
189 #define E1000_RCTL_EN 0x00000002 /* enable */
191 #define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */
192 #define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */
193 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
203 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
213 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
214 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
261 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
263 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
264 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
272 #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */
277 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
284 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
285 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
286 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
288 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
325 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
340 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
341 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
343 /* Constants used to interpret the masked PCI-X bus speed. */
344 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
345 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
346 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
365 /* 1000/H is not supported, nor spec-compliant. */
404 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
411 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
416 #define E1000_TCTL_EN 0x00000002 /* enable Tx */
420 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
424 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
434 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
435 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
523 /* Uncorrectable/correctable ECC Error counts and enable bits */
578 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
580 #define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */
582 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */
597 #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
601 /* This defines the bits that are set in the Interrupt Mask
616 /* Interrupt Mask Set */
639 /* Extended Interrupt Mask Set */
680 /* Enable the counting of descriptors still to be processed. */
727 /* Loop limit on how long we wait for auto-negotiation to complete */
742 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
743 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
744 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
750 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
751 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
754 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
760 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
769 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
775 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
821 #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
822 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
823 #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
832 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
833 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
834 #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
837 #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
864 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
865 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
924 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
929 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
986 /* 1000BASE-T Control Register */
1002 /* 1000BASE-T Status Register */
1025 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1026 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1046 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1153 /* Mask bits for fields in Word 0x24 of the NVM */
1162 /* Mask bits for fields in Word 0x0f of the NVM */
1168 /* Mask bits for fields in Word 0x1a of the NVM */
1171 /* Mask bits for fields in Word 0x03 of the EEPROM */
1192 /* NVM Commands - Microwire */
1196 #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */
1199 /* NVM Commands - SPI */
1203 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1204 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
1231 /* PCI/PCI-X/PCI-EX Config space */
1255 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1306 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1317 * 1 = 50-80M
1318 * 2 = 80-110M
1319 * 3 = 110-140M
1379 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
1382 * 15-5: page
1383 * 4-0: register offset
1401 /* Page 193 - Port Control Registers */
1406 /* Page 194 - KMRN Registers */
1450 /* Tx Rate-Scheduler Config fields */
1466 #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
1467 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1499 #define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */
1502 #define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */
1504 #define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */
1505 #define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */
1516 #define E1000_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */