Lines Matching +full:enable +full:- +full:mask

1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
51 #define CD180_IER       0x02    /* Interrupt Enable Register              */
80 #define GICR_CHAN       0x1C    /* Channel Number Mask                    */
84 #define CAR_CHAN        0x07    /* Channel Number Mask                    */
93 #define RCSR_SCMASK     0x70    /* Special Character Detected Mask        */
110 #define CCR_RCVREN      0x12    /* Receiver Enable                        */
112 #define CCR_XMTREN      0x18    /* Transmitter Enable                     */
114 /* Interrupt Enable Register */
115 #define IER_DSR         0x80    /* Enable interrupt on DSR change         */
116 #define IER_CD          0x40    /* Enable interrupt on CD change          */
117 #define IER_CTS         0x20    /* Enable interrupt on CTS change         */
118 #define IER_RxData      0x10    /* Enable interrupt on Receive Data       */
119 #define IER_RxSC        0x08    /* Enable interrupt on Receive Spec. Char */
120 #define IER_TxRdy       0x04    /* Enable interrupt on TX FIFO empty      */
121 #define IER_TxMpty      0x02    /* Enable interrupt on TX completely empty*/
122 #define IER_RET         0x01    /* Enable interrupt on RX Except. Timeout */
126 #define COR1_ParMMASK   0x60    /* Parity Mode mask                       */
131 #define COR1_StopMASK   0x0C    /* Stop Bits mode mask                    */
135 #define COR1_CHLMASK    0x03    /* Character Length mask                  */
143 #define COR2_TxIBE      0x40    /* Enable In-Band XON/XOFF Flow Control   */
144 #define COR2_ETC        0x20    /* Embedded Tx Commands Enable            */
147 #define COR2_RtsAO      0x04    /* RTS Automatic Output Enable            */
148 #define COR2_CtsAE      0x02    /* CTS Automatic Enable                   */
149 #define COR2_DsrAE      0x01    /* DSR Automatic Enable                   */
154 #define COR3_FCT        0x20    /* Flow-Control Transparency Mode         */
155 #define COR3_SCDE       0x10    /* Special Character Detection Enable     */
156 #define COR3_RxTHMASK   0x0F    /* RX FIFO Threshold value (1-8)          */
167 #define MCOR1_DSRzd     0x80    /* Detect 0->1 transition of DSR          */
168 #define MCOR1_CDzd      0x40    /* Detect 0->1 transition of CD           */
169 #define MCOR1_CTSzd     0x20    /* Detect 0->1 transition of CTS          */
170 #define MCOR1_DTRthMASK 0x0F    /* Automatic DTR FC Threshold (1-8) chars */
173 #define MCOR2_DSRod     0x80    /* Detect 1->0 transition of DSR          */
174 #define MCOR2_CDod      0x40    /* Detect 1->0 transition of CD           */
175 #define MCOR2_CTSod     0x20    /* Detect 1->0 transition of CTS          */