Lines Matching +full:enable +full:- +full:mask
2 * Copyright 2008-2012 Freescale Semiconductor Inc.
40 uint32_t event, mask, force; in fman_get_bmi_err_event() local
42 event = ioread32be(&bmi_rg->fmbm_ievr); in fman_get_bmi_err_event()
43 mask = ioread32be(&bmi_rg->fmbm_ier); in fman_get_bmi_err_event()
44 event &= mask; in fman_get_bmi_err_event()
46 force = ioread32be(&bmi_rg->fmbm_ifr); in fman_get_bmi_err_event()
48 iowrite32be(force & ~event, &bmi_rg->fmbm_ifr); in fman_get_bmi_err_event()
50 iowrite32be(event, &bmi_rg->fmbm_ievr); in fman_get_bmi_err_event()
56 uint32_t event, mask, force; in fman_get_qmi_err_event() local
58 event = ioread32be(&qmi_rg->fmqm_eie); in fman_get_qmi_err_event()
59 mask = ioread32be(&qmi_rg->fmqm_eien); in fman_get_qmi_err_event()
60 event &= mask; in fman_get_qmi_err_event()
63 force = ioread32be(&qmi_rg->fmqm_eif); in fman_get_qmi_err_event()
65 iowrite32be(force & ~event, &qmi_rg->fmqm_eif); in fman_get_qmi_err_event()
67 iowrite32be(event, &qmi_rg->fmqm_eie); in fman_get_qmi_err_event()
73 return ioread32be(&dma_rg->fmdmtcid); in fman_get_dma_com_id()
80 addr = (uint64_t)ioread32be(&dma_rg->fmdmtal); in fman_get_dma_addr()
81 addr |= ((uint64_t)(ioread32be(&dma_rg->fmdmtah)) << 32); in fman_get_dma_addr()
88 uint32_t status, mask; in fman_get_dma_err_event() local
90 status = ioread32be(&dma_rg->fmdmsr); in fman_get_dma_err_event()
91 mask = ioread32be(&dma_rg->fmdmmr); in fman_get_dma_err_event()
93 /* clear DMA_STATUS_BUS_ERR if mask has no DMA_MODE_BER */ in fman_get_dma_err_event()
94 if ((mask & DMA_MODE_BER) != DMA_MODE_BER) in fman_get_dma_err_event()
97 /* clear relevant bits if mask has no DMA_MODE_ECC */ in fman_get_dma_err_event()
98 if ((mask & DMA_MODE_ECC) != DMA_MODE_ECC) in fman_get_dma_err_event()
105 iowrite32be(status, &dma_rg->fmdmsr); in fman_get_dma_err_event()
114 event = ioread32be(&fpm_rg->fmfp_ee); in fman_get_fpm_err_event()
116 iowrite32be(event, &fpm_rg->fmfp_ee); in fman_get_fpm_err_event()
122 uint32_t event, mask; in fman_get_muram_err_event() local
124 event = ioread32be(&fpm_rg->fm_rcr); in fman_get_muram_err_event()
125 mask = ioread32be(&fpm_rg->fm_rie); in fman_get_muram_err_event()
128 iowrite32be(event & ~FPM_RAM_IRAM_ECC, &fpm_rg->fm_rcr); in fman_get_muram_err_event()
130 if ((mask & FPM_MURAM_ECC_ERR_EX_EN)) in fman_get_muram_err_event()
138 uint32_t event, mask; in fman_get_iram_err_event() local
140 event = ioread32be(&fpm_rg->fm_rcr) ; in fman_get_iram_err_event()
141 mask = ioread32be(&fpm_rg->fm_rie); in fman_get_iram_err_event()
144 &fpm_rg->fm_rcr); in fman_get_iram_err_event()
146 if ((mask & FPM_IRAM_ECC_ERR_EX_EN)) in fman_get_iram_err_event()
154 uint32_t event, mask, force; in fman_get_qmi_event() local
156 event = ioread32be(&qmi_rg->fmqm_ie); in fman_get_qmi_event()
157 mask = ioread32be(&qmi_rg->fmqm_ien); in fman_get_qmi_event()
158 event &= mask; in fman_get_qmi_event()
160 force = ioread32be(&qmi_rg->fmqm_if); in fman_get_qmi_event()
162 iowrite32be(force & ~event, &qmi_rg->fmqm_if); in fman_get_qmi_event()
164 iowrite32be(event, &qmi_rg->fmqm_ie); in fman_get_qmi_event()
189 frac = ((uint64_t)ts_freq << 16) - ((uint64_t)intgr << 16) * fm_clk_freq; in fman_enable_time_stamp()
195 iowrite32be(tmp, &fpm_rg->fmfp_tsc2); in fman_enable_time_stamp()
197 /* enable timestamp with original clock */ in fman_enable_time_stamp()
198 iowrite32be(FPM_TS_CTL_EN, &fpm_rg->fmfp_tsc1); in fman_enable_time_stamp()
203 return ioread32be(&fpm_rg->fm_epi); in fman_get_fpm_error_interrupts()
211 iowrite32be(0x40000000, &fpm_rg->fmfp_extc); in fman_set_erratum_10gmac_a004_wa()
213 while ((ioread32be(&fpm_rg->fmfp_extc) & 0x40000000) && --timeout) in fman_set_erratum_10gmac_a004_wa()
217 return -EBUSY; in fman_set_erratum_10gmac_a004_wa()
225 iowrite32be(enable_events, &fpm_rg->fmfp_cee[event_reg_id]); in fman_set_ctrl_intr()
230 return ioread32be(&fpm_rg->fmfp_cee[event_reg_id]); in fman_get_ctrl_intr()
241 /*TODO - maybe to put CTL# according to another criteria*/ in fman_set_num_of_riscs_per_port()
247 iowrite32be(tmp, &fpm_rg->fmfp_prc); in fman_set_num_of_riscs_per_port()
276 iowrite32be(tmp, &fpm_rg->fmfp_prc); in fman_set_order_restoration_per_port()
281 return (uint8_t)ioread32be(&qmi_rg->fmqm_gc); in fman_get_qmi_deq_th()
286 return (uint8_t)(ioread32be(&qmi_rg->fmqm_gc) >> 8); in fman_get_qmi_enq_th()
293 tmp_reg = ioread32be(&qmi_rg->fmqm_gc); in fman_set_qmi_enq_th()
296 iowrite32be(tmp_reg, &qmi_rg->fmqm_gc); in fman_set_qmi_enq_th()
303 tmp_reg = ioread32be(&qmi_rg->fmqm_gc); in fman_set_qmi_deq_th()
306 iowrite32be(tmp_reg, &qmi_rg->fmqm_gc); in fman_set_qmi_deq_th()
311 iowrite32be(0, &fpm_rg->fmfp_mxd); in fman_qmi_disable_dispatch_limit()
324 tmp = ioread32be(&fman_rg->dma_rg->fmdmplr[port_id / 2]); in fman_set_liodn_per_port()
332 iowrite32be(tmp, &fman_rg->dma_rg->fmdmplr[port_id / 2]); in fman_set_liodn_per_port()
334 &fman_rg->bmi_rg->fmbm_spliodn[port_id - 1]); in fman_set_liodn_per_port()
339 return (bool)!!(ioread32be(&fpm_rg->fmfp_ps[port_id]) & FPM_PS_STALLED); in fman_is_port_stalled()
348 iowrite32be(tmp, &fpm_rg->fmfp_prc); in fman_resume_stalled_port()
355 /* Get the relevant bit mask */ in fman_reset_mac()
365 return -EINVAL; in fman_reset_mac()
394 return -EINVAL; in fman_reset_mac()
398 iowrite32be(msk, &fpm_rg->fm_rstc); in fman_reset_mac()
399 while ((ioread32be(&fpm_rg->fm_rstc) & msk) && --timeout) in fman_reset_mac()
403 return -EBUSY; in fman_reset_mac()
414 tmp_reg = ioread32be(&bmi_rg->fmbm_pfs[port_id - 1]); in fman_get_size_of_fifo()
422 reg = ioread32be(&bmi_rg->fmbm_cfg1); in fman_get_total_fifo_size()
435 tmp_reg = ioread32be(&bmi_rg->fmbm_pfs[port_id-1]); in fman_get_size_of_extra_fifo()
451 tmp = (uint32_t)((sz_fifo / FMAN_BMI_FIFO_UNITS - 1) | in fman_set_size_of_fifo()
454 iowrite32be(tmp, &bmi_rg->fmbm_pfs[port_id - 1]); in fman_set_size_of_fifo()
464 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]); in fman_get_num_of_tasks()
476 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]); in fman_get_num_extra_tasks()
492 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) & in fman_set_num_of_tasks()
494 tmp |= (uint32_t)(((num_tasks - 1) << BMI_NUM_OF_TASKS_SHIFT) | in fman_set_num_of_tasks()
496 iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]); in fman_set_num_of_tasks()
506 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]); in fman_get_num_of_dmas()
518 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]); in fman_get_num_extra_dmas()
535 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) & in fman_set_num_of_open_dmas()
537 tmp |= (uint32_t)(((num_open_dmas-1) << BMI_NUM_OF_DMAS_SHIFT) | in fman_set_num_of_open_dmas()
539 iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]); in fman_set_num_of_open_dmas()
545 tmp = ioread32be(&bmi_rg->fmbm_cfg2) & ~BMI_CFG2_DMAS_MASK; in fman_set_num_of_open_dmas()
546 tmp |= (uint32_t)(total_num_dmas - 1) << BMI_CFG2_DMAS_SHIFT; in fman_set_num_of_open_dmas()
547 iowrite32be(tmp, &bmi_rg->fmbm_cfg2); in fman_set_num_of_open_dmas()
560 tmp = ioread32be(&bmi_rg->fmbm_spliodn[port_id-1]); in fman_set_vsp_window()
563 iowrite32be(tmp, &bmi_rg->fmbm_spliodn[port_id-1]); in fman_set_vsp_window()
589 cfg->catastrophic_err = DEFAULT_CATASTROPHIC_ERR; in fman_defconfig()
590 cfg->dma_err = DEFAULT_DMA_ERR; in fman_defconfig()
591 cfg->halt_on_external_activ = DEFAULT_HALT_ON_EXTERNAL_ACTIVATION; in fman_defconfig()
592 cfg->halt_on_unrecov_ecc_err = DEFAULT_HALT_ON_UNRECOVERABLE_ECC_ERROR; in fman_defconfig()
593 cfg->en_iram_test_mode = FALSE; in fman_defconfig()
594 cfg->en_muram_test_mode = FALSE; in fman_defconfig()
595 cfg->external_ecc_rams_enable = DEFAULT_EXTERNAL_ECC_RAMS_ENABLE; in fman_defconfig()
600 cfg->dma_aid_override = DEFAULT_AID_OVERRIDE; in fman_defconfig()
601 cfg->dma_aid_mode = DEFAULT_AID_MODE; in fman_defconfig()
602 cfg->dma_comm_qtsh_clr_emer = DEFAULT_DMA_COMM_Q_LOW; in fman_defconfig()
603 cfg->dma_comm_qtsh_asrt_emer = DEFAULT_DMA_COMM_Q_HIGH; in fman_defconfig()
604 cfg->dma_cache_override = DEFAULT_CACHE_OVERRIDE; in fman_defconfig()
605 cfg->dma_cam_num_of_entries = DEFAULT_DMA_CAM_NUM_OF_ENTRIES; in fman_defconfig()
606 cfg->dma_dbg_cnt_mode = DEFAULT_DMA_DBG_CNT_MODE; in fman_defconfig()
607 cfg->dma_en_emergency = DEFAULT_DMA_EN_EMERGENCY; in fman_defconfig()
608 cfg->dma_sos_emergency = DEFAULT_DMA_SOS_EMERGENCY; in fman_defconfig()
609 cfg->dma_watchdog = DEFAULT_DMA_WATCHDOG; in fman_defconfig()
610 cfg->dma_en_emergency_smoother = DEFAULT_DMA_EN_EMERGENCY_SMOOTHER; in fman_defconfig()
611 cfg->dma_emergency_switch_counter = DEFAULT_DMA_EMERGENCY_SWITCH_COUNTER; in fman_defconfig()
612 cfg->disp_limit_tsh = DEFAULT_DISP_LIMIT; in fman_defconfig()
613 cfg->prs_disp_tsh = DEFAULT_PRS_DISP_TH; in fman_defconfig()
614 cfg->plcr_disp_tsh = DEFAULT_PLCR_DISP_TH; in fman_defconfig()
615 cfg->kg_disp_tsh = DEFAULT_KG_DISP_TH; in fman_defconfig()
616 cfg->bmi_disp_tsh = DEFAULT_BMI_DISP_TH; in fman_defconfig()
617 cfg->qmi_enq_disp_tsh = DEFAULT_QMI_ENQ_DISP_TH; in fman_defconfig()
618 cfg->qmi_deq_disp_tsh = DEFAULT_QMI_DEQ_DISP_TH; in fman_defconfig()
619 cfg->fm_ctl1_disp_tsh = DEFAULT_FM_CTL1_DISP_TH; in fman_defconfig()
620 cfg->fm_ctl2_disp_tsh = DEFAULT_FM_CTL2_DISP_TH; in fman_defconfig()
622 cfg->pedantic_dma = FALSE; in fman_defconfig()
623 cfg->tnum_aging_period = DEFAULT_TNUM_AGING_PERIOD; in fman_defconfig()
624 cfg->dma_stop_on_bus_error = FALSE; in fman_defconfig()
625 cfg->qmi_deq_option_support = FALSE; in fman_defconfig()
635 tmp_reg = ioread32be(&fman_rg->bmi_rg->fmbm_cfg1); in fman_regconfig()
636 cfg->total_fifo_size = in fman_regconfig()
639 tmp_reg = ioread32be(&fman_rg->bmi_rg->fmbm_cfg2); in fman_regconfig()
640 cfg->total_num_of_tasks = in fman_regconfig()
643 tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmtr); in fman_regconfig()
644 cfg->dma_comm_qtsh_asrt_emer = (uint8_t)(tmp_reg >> DMA_THRESH_COMMQ_SHIFT); in fman_regconfig()
646 tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmhy); in fman_regconfig()
647 cfg->dma_comm_qtsh_clr_emer = (uint8_t)(tmp_reg >> DMA_THRESH_COMMQ_SHIFT); in fman_regconfig()
649 tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmmr); in fman_regconfig()
650 …cfg->dma_cache_override = (enum fman_dma_cache_override)((tmp_reg & DMA_MODE_CACHE_OR_MASK) >… in fman_regconfig()
651 …cfg->dma_cam_num_of_entries = (uint8_t)((((tmp_reg & DMA_MODE_CEN_MASK) >> DMA_MODE_CEN_SHIFT) +1… in fman_regconfig()
652 cfg->dma_aid_override = (bool)((tmp_reg & DMA_MODE_AID_OR)? TRUE:FALSE); in fman_regconfig()
653 …cfg->dma_dbg_cnt_mode = (enum fman_dma_dbg_cnt_mode)((tmp_reg & DMA_MODE_DBG_MASK) >> DMA_M… in fman_regconfig()
654 cfg->dma_en_emergency = (bool)((tmp_reg & DMA_MODE_EB)? TRUE : FALSE); in fman_regconfig()
656 tmp_reg = ioread32be(&fman_rg->fpm_rg->fmfp_mxd); in fman_regconfig()
657 … cfg->disp_limit_tsh = (uint8_t)((tmp_reg & FPM_DISP_LIMIT_MASK) >> FPM_DISP_LIMIT_SHIFT); in fman_regconfig()
659 tmp_reg = ioread32be(&fman_rg->fpm_rg->fmfp_dist1); in fman_regconfig()
660 cfg->prs_disp_tsh = (uint8_t)((tmp_reg & FPM_THR1_PRS_MASK ) >> FPM_THR1_PRS_SHIFT); in fman_regconfig()
661 cfg->plcr_disp_tsh = (uint8_t)((tmp_reg & FPM_THR1_KG_MASK ) >> FPM_THR1_KG_SHIFT); in fman_regconfig()
662 … cfg->kg_disp_tsh = (uint8_t)((tmp_reg & FPM_THR1_PLCR_MASK ) >> FPM_THR1_PLCR_SHIFT); in fman_regconfig()
663 cfg->bmi_disp_tsh = (uint8_t)((tmp_reg & FPM_THR1_BMI_MASK ) >> FPM_THR1_BMI_SHIFT); in fman_regconfig()
665 tmp_reg = ioread32be(&fman_rg->fpm_rg->fmfp_dist2); in fman_regconfig()
666 …cfg->qmi_enq_disp_tsh = (uint8_t)((tmp_reg & FPM_THR2_QMI_ENQ_MASK ) >> FPM_THR2_QMI_ENQ_SH… in fman_regconfig()
667 …cfg->qmi_deq_disp_tsh = (uint8_t)((tmp_reg & FPM_THR2_QMI_DEQ_MASK ) >> FPM_THR2_QMI_DEQ_SH… in fman_regconfig()
668 …cfg->fm_ctl1_disp_tsh = (uint8_t)((tmp_reg & FPM_THR2_FM_CTL1_MASK ) >> FPM_THR2_FM_CTL1_SH… in fman_regconfig()
669 …cfg->fm_ctl2_disp_tsh = (uint8_t)((tmp_reg & FPM_THR2_FM_CTL2_MASK ) >> FPM_THR2_FM_CTL2_SH… in fman_regconfig()
671 tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmsetr); in fman_regconfig()
672 cfg->dma_sos_emergency = tmp_reg; in fman_regconfig()
674 tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmwcr); in fman_regconfig()
675 cfg->dma_watchdog = tmp_reg/cfg->clk_freq; in fman_regconfig()
677 tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmemsr); in fman_regconfig()
678 cfg->dma_en_emergency_smoother = (bool)((tmp_reg & DMA_EMSR_EMSTR_MASK)? TRUE : FALSE); in fman_regconfig()
679 cfg->dma_emergency_switch_counter = (tmp_reg & DMA_EMSR_EMSTR_MASK); in fman_regconfig()
684 iowrite32be(FPM_RSTC_FM_RESET, &fpm_rg->fm_rstc); in fman_reset()
692 @Param[in] h_Fm - FM module descriptor
704 /* oren - check!!! */ in fman_dma_init()
707 iowrite32be(ioread32be(&dma_rg->fmdmsr) | tmp_reg, in fman_dma_init()
708 &dma_rg->fmdmsr); in fman_dma_init()
712 tmp_reg |= cfg->dma_cache_override << DMA_MODE_CACHE_OR_SHIFT; in fman_dma_init()
713 if (cfg->dma_aid_override) in fman_dma_init()
715 if (cfg->exceptions & FMAN_EX_DMA_BUS_ERROR) in fman_dma_init()
717 if ((cfg->exceptions & FMAN_EX_DMA_SYSTEM_WRITE_ECC) | in fman_dma_init()
718 (cfg->exceptions & FMAN_EX_DMA_READ_ECC) | in fman_dma_init()
719 (cfg->exceptions & FMAN_EX_DMA_FM_WRITE_ECC)) in fman_dma_init()
721 if (cfg->dma_stop_on_bus_error) in fman_dma_init()
723 if(cfg->dma_axi_dbg_num_of_beats) in fman_dma_init()
725 ((cfg->dma_axi_dbg_num_of_beats - 1) << DMA_MODE_AXI_DBG_SHIFT)); in fman_dma_init()
727 if (cfg->dma_en_emergency) { in fman_dma_init()
728 tmp_reg |= cfg->dma_emergency_bus_select; in fman_dma_init()
729 tmp_reg |= cfg->dma_emergency_level << DMA_MODE_EMER_LVL_SHIFT; in fman_dma_init()
730 if (cfg->dma_en_emergency_smoother) in fman_dma_init()
731 iowrite32be(cfg->dma_emergency_switch_counter, in fman_dma_init()
732 &dma_rg->fmdmemsr); in fman_dma_init()
734 tmp_reg |= ((cfg->dma_cam_num_of_entries / DMA_CAM_UNITS) - 1) << in fman_dma_init()
737 tmp_reg |= cfg->dma_dbg_cnt_mode << DMA_MODE_DBG_SHIFT; in fman_dma_init()
738 tmp_reg |= cfg->dma_aid_mode << DMA_MODE_AID_MODE_SHIFT; in fman_dma_init()
740 if (cfg->pedantic_dma) in fman_dma_init()
743 iowrite32be(tmp_reg, &dma_rg->fmdmmr); in fman_dma_init()
746 tmp_reg = ((uint32_t)cfg->dma_comm_qtsh_asrt_emer << in fman_dma_init()
748 ((uint32_t)cfg->dma_read_buf_tsh_asrt_emer << in fman_dma_init()
750 ((uint32_t)cfg->dma_write_buf_tsh_asrt_emer); in fman_dma_init()
752 iowrite32be(tmp_reg, &dma_rg->fmdmtr); in fman_dma_init()
755 tmp_reg = ((uint32_t)cfg->dma_comm_qtsh_clr_emer << in fman_dma_init()
757 ((uint32_t)cfg->dma_read_buf_tsh_clr_emer << in fman_dma_init()
759 ((uint32_t)cfg->dma_write_buf_tsh_clr_emer); in fman_dma_init()
761 iowrite32be(tmp_reg, &dma_rg->fmdmhy); in fman_dma_init()
764 iowrite32be(cfg->dma_sos_emergency, &dma_rg->fmdmsetr); in fman_dma_init()
767 iowrite32be((cfg->dma_watchdog * cfg->clk_freq), in fman_dma_init()
768 &dma_rg->fmdmwcr); in fman_dma_init()
770 iowrite32be(cfg->cam_base_addr, &dma_rg->fmdmebcr); in fman_dma_init()
783 tmp_reg = (uint32_t)(cfg->disp_limit_tsh << FPM_DISP_LIMIT_SHIFT); in fman_fpm_init()
784 iowrite32be(tmp_reg, &fpm_rg->fmfp_mxd); in fman_fpm_init()
786 tmp_reg = (((uint32_t)cfg->prs_disp_tsh << FPM_THR1_PRS_SHIFT) | in fman_fpm_init()
787 ((uint32_t)cfg->kg_disp_tsh << FPM_THR1_KG_SHIFT) | in fman_fpm_init()
788 ((uint32_t)cfg->plcr_disp_tsh << FPM_THR1_PLCR_SHIFT) | in fman_fpm_init()
789 ((uint32_t)cfg->bmi_disp_tsh << FPM_THR1_BMI_SHIFT)); in fman_fpm_init()
790 iowrite32be(tmp_reg, &fpm_rg->fmfp_dist1); in fman_fpm_init()
792 tmp_reg = (((uint32_t)cfg->qmi_enq_disp_tsh << FPM_THR2_QMI_ENQ_SHIFT) | in fman_fpm_init()
793 ((uint32_t)cfg->qmi_deq_disp_tsh << FPM_THR2_QMI_DEQ_SHIFT) | in fman_fpm_init()
794 ((uint32_t)cfg->fm_ctl1_disp_tsh << FPM_THR2_FM_CTL1_SHIFT) | in fman_fpm_init()
795 ((uint32_t)cfg->fm_ctl2_disp_tsh << FPM_THR2_FM_CTL2_SHIFT)); in fman_fpm_init()
796 iowrite32be(tmp_reg, &fpm_rg->fmfp_dist2); in fman_fpm_init()
803 /* enable interrupts */ in fman_fpm_init()
804 if (cfg->exceptions & FMAN_EX_FPM_STALL_ON_TASKS) in fman_fpm_init()
806 if (cfg->exceptions & FMAN_EX_FPM_SINGLE_ECC) in fman_fpm_init()
808 if (cfg->exceptions & FMAN_EX_FPM_DOUBLE_ECC) in fman_fpm_init()
810 tmp_reg |= (cfg->catastrophic_err << FPM_EV_MASK_CAT_ERR_SHIFT); in fman_fpm_init()
811 tmp_reg |= (cfg->dma_err << FPM_EV_MASK_DMA_ERR_SHIFT); in fman_fpm_init()
812 if (!cfg->halt_on_external_activ) in fman_fpm_init()
814 if (!cfg->halt_on_unrecov_ecc_err) in fman_fpm_init()
816 iowrite32be(tmp_reg, &fpm_rg->fmfp_ee); in fman_fpm_init()
819 for (i = 0; i < cfg->num_of_fman_ctrl_evnt_regs; i++) in fman_fpm_init()
820 iowrite32be(0xFFFFFFFF, &fpm_rg->fmfp_cev[i]); in fman_fpm_init()
822 /* RAM ECC - enable and clear events*/ in fman_fpm_init()
827 /* Rams enable not effected by RCR bit, but by a COP configuration */ in fman_fpm_init()
828 if (cfg->external_ecc_rams_enable) in fman_fpm_init()
831 /* enable test mode */ in fman_fpm_init()
832 if (cfg->en_muram_test_mode) in fman_fpm_init()
834 if (cfg->en_iram_test_mode) in fman_fpm_init()
836 iowrite32be(tmp_reg, &fpm_rg->fm_rcr); in fman_fpm_init()
839 if (cfg->exceptions & FMAN_EX_IRAM_ECC) { in fman_fpm_init()
843 if (cfg->exceptions & FMAN_EX_NURAM_ECC) { in fman_fpm_init()
847 iowrite32be(tmp_reg, &fpm_rg->fm_rie); in fman_fpm_init()
861 tmp_reg = cfg->fifo_base_addr; in fman_bmi_init()
864 tmp_reg |= ((cfg->total_fifo_size / FMAN_BMI_FIFO_UNITS - 1) << in fman_bmi_init()
866 iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg1); in fman_bmi_init()
868 tmp_reg = ((uint32_t)(cfg->total_num_of_tasks - 1) << in fman_bmi_init()
871 iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg2); in fman_bmi_init()
873 /* define unmaskable exceptions, enable and clear events */ in fman_bmi_init()
879 &bmi_rg->fmbm_ievr); in fman_bmi_init()
881 if (cfg->exceptions & FMAN_EX_BMI_LIST_RAM_ECC) in fman_bmi_init()
883 if (cfg->exceptions & FMAN_EX_BMI_PIPELINE_ECC) in fman_bmi_init()
885 if (cfg->exceptions & FMAN_EX_BMI_STATISTICS_RAM_ECC) in fman_bmi_init()
887 if (cfg->exceptions & FMAN_EX_BMI_DISPATCH_RAM_ECC) in fman_bmi_init()
889 iowrite32be(tmp_reg, &bmi_rg->fmbm_ier); in fman_bmi_init()
905 &qmi_rg->fmqm_eie); in fman_qmi_init()
907 if (cfg->exceptions & FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID) in fman_qmi_init()
909 if (cfg->exceptions & FMAN_EX_QMI_DOUBLE_ECC) in fman_qmi_init()
911 /* enable events */ in fman_qmi_init()
912 iowrite32be(tmp_reg, &qmi_rg->fmqm_eien); in fman_qmi_init()
914 if (cfg->tnum_aging_period) { in fman_qmi_init()
917 (cfg->tnum_aging_period * cfg->clk_freq); in fman_qmi_init()
928 iowrite32be(tmp_reg, &qmi_rg->fmqm_tapc); in fman_qmi_init()
932 iowrite32be(QMI_INTR_EN_SINGLE_ECC, &qmi_rg->fmqm_ie); in fman_qmi_init()
933 if (cfg->exceptions & FMAN_EX_QMI_SINGLE_ECC) in fman_qmi_init()
935 /* enable events */ in fman_qmi_init()
936 iowrite32be(tmp_reg, &qmi_rg->fmqm_ien); in fman_qmi_init()
946 /* Enable all modules */ in fman_enable()
948 /* clear & enable global counters - calculate reg and save for later, in fman_enable()
949 because it's the same reg for QMI enable */ in fman_enable()
951 if (cfg->qmi_deq_option_support) in fman_enable()
952 cfg_reg |= (uint32_t)(((cfg->qmi_def_tnums_thresh) << 8) | in fman_enable()
953 (uint32_t)cfg->qmi_def_tnums_thresh); in fman_enable()
955 iowrite32be(BMI_INIT_START, &fman_rg->bmi_rg->fmbm_init); in fman_enable()
957 &fman_rg->qmi_rg->fmqm_gc); in fman_enable()
965 iowrite32be(0, &fman_rg->bmi_rg->fmbm_init); in fman_free_resources()
966 iowrite32be(0, &fman_rg->qmi_rg->fmqm_gc); in fman_free_resources()
969 iowrite32be(0, &fman_rg->bmi_rg->fmbm_cfg2); in fman_free_resources()
970 iowrite32be(0, &fman_rg->bmi_rg->fmbm_cfg1); in fman_free_resources()
973 iowrite32be(0, &fman_rg->fpm_rg->fm_rcr); in fman_free_resources()
977 /* API Run-time Control uint functions */
981 return ioread32be(&fpm_rg->fm_npi); in fman_get_normal_pending()
988 event = ioread32be(&fpm_rg->fmfp_fcev[reg_id]) & in fman_get_controller_event()
989 ioread32be(&fpm_rg->fmfp_cee[reg_id]); in fman_get_controller_event()
990 iowrite32be(event, &fpm_rg->fmfp_cev[reg_id]); in fman_get_controller_event()
997 return ioread32be(&fpm_rg->fm_epi); in fman_get_error_pending()
1010 shift = (uint8_t)(32 - 4 * ((i % 8) + 1)); in fman_set_ports_bandwidth()
1011 tmp |= ((weights[i] - 1) << shift); in fman_set_ports_bandwidth()
1014 iowrite32be(tmp, &bmi_rg->fmbm_arb[i / 8]); in fman_set_ports_bandwidth()
1024 tmp = ioread32be(&fpm_rg->fm_rcr); in fman_enable_rams_ecc()
1027 &fpm_rg->fm_rcr); in fman_enable_rams_ecc()
1031 &fpm_rg->fm_rcr); in fman_enable_rams_ecc()
1038 tmp = ioread32be(&fpm_rg->fm_rcr); in fman_disable_rams_ecc()
1041 &fpm_rg->fm_rcr); in fman_disable_rams_ecc()
1044 &fpm_rg->fm_rcr); in fman_disable_rams_ecc()
1049 bool enable) in fman_set_exception() argument
1055 tmp = ioread32be(&fman_rg->dma_rg->fmdmmr); in fman_set_exception()
1056 if (enable) in fman_set_exception()
1061 iowrite32be(tmp, &fman_rg->dma_rg->fmdmmr); in fman_set_exception()
1066 tmp = ioread32be(&fman_rg->dma_rg->fmdmmr); in fman_set_exception()
1067 if (enable) in fman_set_exception()
1071 iowrite32be(tmp, &fman_rg->dma_rg->fmdmmr); in fman_set_exception()
1074 tmp = ioread32be(&fman_rg->fpm_rg->fmfp_ee); in fman_set_exception()
1075 if (enable) in fman_set_exception()
1079 iowrite32be(tmp, &fman_rg->fpm_rg->fmfp_ee); in fman_set_exception()
1082 tmp = ioread32be(&fman_rg->fpm_rg->fmfp_ee); in fman_set_exception()
1083 if (enable) in fman_set_exception()
1087 iowrite32be(tmp, &fman_rg->fpm_rg->fmfp_ee); in fman_set_exception()
1090 tmp = ioread32be(&fman_rg->fpm_rg->fmfp_ee); in fman_set_exception()
1091 if (enable) in fman_set_exception()
1095 iowrite32be(tmp, &fman_rg->fpm_rg->fmfp_ee); in fman_set_exception()
1098 tmp = ioread32be(&fman_rg->qmi_rg->fmqm_ien); in fman_set_exception()
1099 if (enable) in fman_set_exception()
1103 iowrite32be(tmp, &fman_rg->qmi_rg->fmqm_ien); in fman_set_exception()
1106 tmp = ioread32be(&fman_rg->qmi_rg->fmqm_eien); in fman_set_exception()
1107 if (enable) in fman_set_exception()
1111 iowrite32be(tmp, &fman_rg->qmi_rg->fmqm_eien); in fman_set_exception()
1114 tmp = ioread32be(&fman_rg->qmi_rg->fmqm_eien); in fman_set_exception()
1115 if (enable) in fman_set_exception()
1119 iowrite32be(tmp, &fman_rg->qmi_rg->fmqm_eien); in fman_set_exception()
1122 tmp = ioread32be(&fman_rg->bmi_rg->fmbm_ier); in fman_set_exception()
1123 if (enable) in fman_set_exception()
1127 iowrite32be(tmp, &fman_rg->bmi_rg->fmbm_ier); in fman_set_exception()
1130 tmp = ioread32be(&fman_rg->bmi_rg->fmbm_ier); in fman_set_exception()
1131 if (enable) in fman_set_exception()
1135 iowrite32be(tmp, &fman_rg->bmi_rg->fmbm_ier); in fman_set_exception()
1138 tmp = ioread32be(&fman_rg->bmi_rg->fmbm_ier); in fman_set_exception()
1139 if (enable) in fman_set_exception()
1143 iowrite32be(tmp, &fman_rg->bmi_rg->fmbm_ier); in fman_set_exception()
1146 tmp = ioread32be(&fman_rg->bmi_rg->fmbm_ier); in fman_set_exception()
1147 if (enable) in fman_set_exception()
1151 iowrite32be(tmp, &fman_rg->bmi_rg->fmbm_ier); in fman_set_exception()
1154 tmp = ioread32be(&fman_rg->fpm_rg->fm_rie); in fman_set_exception()
1155 if (enable) { in fman_set_exception()
1156 /* enable ECC if not enabled */ in fman_set_exception()
1157 fman_enable_rams_ecc(fman_rg->fpm_rg); in fman_set_exception()
1158 /* enable ECC interrupts */ in fman_set_exception()
1163 fman_disable_rams_ecc(fman_rg->fpm_rg); in fman_set_exception()
1166 iowrite32be(tmp, &fman_rg->fpm_rg->fm_rie); in fman_set_exception()
1169 tmp = ioread32be(&fman_rg->fpm_rg->fm_rie); in fman_set_exception()
1170 if (enable) { in fman_set_exception()
1171 /* enable ECC if not enabled */ in fman_set_exception()
1172 fman_enable_rams_ecc(fman_rg->fpm_rg); in fman_set_exception()
1173 /* enable ECC interrupts */ in fman_set_exception()
1178 fman_disable_rams_ecc(fman_rg->fpm_rg); in fman_set_exception()
1181 iowrite32be(tmp, &fman_rg->fpm_rg->fm_rie); in fman_set_exception()
1184 return -EINVAL; in fman_set_exception()
1195 tmp = ioread32be(&fpm_rg->fm_ip_rev_1); in fman_get_revision()
1208 ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_etfc); in fman_get_counter()
1211 ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dtfc); in fman_get_counter()
1214 ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dc0); in fman_get_counter()
1217 ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dc1); in fman_get_counter()
1220 ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dc2); in fman_get_counter()
1223 ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dc3); in fman_get_counter()
1226 ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dfdc); in fman_get_counter()
1229 ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dfcc); in fman_get_counter()
1232 ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dffc); in fman_get_counter()
1235 ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dcc); in fman_get_counter()
1247 /* When applicable (when there is an 'enable counters' bit, in fman_modify_counter()
1260 if (!(ioread32be(&fman_rg->qmi_rg->fmqm_gc) & in fman_modify_counter()
1262 return -EINVAL; in fman_modify_counter()
1270 iowrite32be(val, &fman_rg->qmi_rg->fmqm_etfc); in fman_modify_counter()
1273 iowrite32be(val, &fman_rg->qmi_rg->fmqm_dtfc); in fman_modify_counter()
1276 iowrite32be(val, &fman_rg->qmi_rg->fmqm_dc0); in fman_modify_counter()
1279 iowrite32be(val, &fman_rg->qmi_rg->fmqm_dc1); in fman_modify_counter()
1282 iowrite32be(val, &fman_rg->qmi_rg->fmqm_dc2); in fman_modify_counter()
1285 iowrite32be(val, &fman_rg->qmi_rg->fmqm_dc3); in fman_modify_counter()
1288 iowrite32be(val, &fman_rg->qmi_rg->fmqm_dfdc); in fman_modify_counter()
1291 iowrite32be(val, &fman_rg->qmi_rg->fmqm_dfcc); in fman_modify_counter()
1294 iowrite32be(val, &fman_rg->qmi_rg->fmqm_dffc); in fman_modify_counter()
1297 iowrite32be(val, &fman_rg->qmi_rg->fmqm_dcc); in fman_modify_counter()
1300 iowrite32be(val, &fman_rg->dma_rg->fmdmsefrc); in fman_modify_counter()
1303 iowrite32be(val, &fman_rg->dma_rg->fmdmsqfrc); in fman_modify_counter()
1306 iowrite32be(val, &fman_rg->dma_rg->fmdmssrc); in fman_modify_counter()
1316 bool enable) in fman_set_dma_emergency() argument
1322 if (enable) in fman_set_dma_emergency()
1323 iowrite32be(ioread32be(&dma_rg->fmdmmr) | msk, in fman_set_dma_emergency()
1324 &dma_rg->fmdmmr); in fman_set_dma_emergency()
1326 iowrite32be(ioread32be(&dma_rg->fmdmmr) & ~msk, in fman_set_dma_emergency()
1327 &dma_rg->fmdmmr); in fman_set_dma_emergency()
1334 tmp = ioread32be(&dma_rg->fmdmmr) | in fman_set_dma_ext_bus_pri()
1337 iowrite32be(tmp, &dma_rg->fmdmmr); in fman_set_dma_ext_bus_pri()
1342 return ioread32be(&dma_rg->fmdmsr); in fman_get_dma_status()
1351 &fman_rg->qmi_rg->fmqm_eif); in fman_force_intr()
1355 &fman_rg->qmi_rg->fmqm_if); in fman_force_intr()
1359 &fman_rg->qmi_rg->fmqm_eif); in fman_force_intr()
1363 &fman_rg->bmi_rg->fmbm_ifr); in fman_force_intr()
1367 &fman_rg->bmi_rg->fmbm_ifr); in fman_force_intr()
1371 &fman_rg->bmi_rg->fmbm_ifr); in fman_force_intr()
1375 &fman_rg->bmi_rg->fmbm_ifr); in fman_force_intr()
1384 return (bool)!!(ioread32be(&qmi_rg->fmqm_gs) & QMI_GS_HALT_NOT_BUSY); in fman_is_qmi_halt_not_busy_state()
1390 tmp = ioread32be(&fpm_rg->fmfp_ee); in fman_resume()
1397 iowrite32be(tmp, &fpm_rg->fmfp_ee); in fman_resume()