| /linux/drivers/clk/zynqmp/ |
| H A D | divider.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC Divider support
5 * Copyright (C) 2016-2019 Xilinx
7 * Adjustable divider clock implementation
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
16 * DOC: basic adjustable divider clock that cannot gate
18 * Traits of this clock:
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
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| /linux/drivers/clk/baikal-t1/ |
| H A D | ccu-div.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Baikal-T1 CCU Dividers interface driver
10 #include <linux/clk-provider.h>
17 * CCU Divider private clock IDs
18 * @CCU_SYS_SATA_CLK: CCU SATA internal clock
19 * @CCU_SYS_XGMAC_CLK: CCU XGMAC internal clock
21 #define CCU_SYS_SATA_CLK -1
22 #define CCU_SYS_XGMAC_CLK -2
25 * CCU Divider private flags
26 * @CCU_DIV_BASIC: Basic divider clock required by the kernel as early as
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| /linux/include/dt-bindings/clock/ |
| H A D | tegra234-clock.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
9 * @defgroup bpmp_clock_ids Clock ID's
36 /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
52 * divided by the divider controlled by ACLK_CLK_DIVISOR in
56 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */
58 /** @brief clock recovered from EAVB input */
60 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */
62 /** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */
64 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */
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| H A D | tegra186-clock.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 * @defgroup clock_ids Clock Identifiers
235 * @defgroup nafll_clks NAFLL clock sources
355 * pwrclk. @warning: This is almost certainly not the clock you think
356 * it is. If you're looking for the clock of the graphics engine, see
362 /** @brief output of the divider IPFS_CLK_DIVISOR */
417 * @brief controls the EMC clock frequency.
418 * @details Doing a clk_set_rate on this clock will select the
419 * appropriate clock source, program the source rate and execute a
420 * specific sequence to switch to the new clock source for both memory
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | xgene.txt | 1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
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| H A D | keystone-pll.txt | 2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
7 This binding uses the common clock binding[1].
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
14 - clocks : parent clock phandle
15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
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| H A D | dove-divider-clock.txt | 1 PLL divider based Dove clocks
9 ID Clock
10 -------------
11 0 AXI bus clock
12 1 GPU clock
13 2 VMeta clock
14 3 LCD clock
17 - compatible : shall be "marvell,dove-divider-clock"
18 - reg : shall be the register address of the Core PLL and Clock Divider
20 Core PLL and Clock Divider Control 1 register. Thus, it will have
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| H A D | nspire-clock.txt | 1 TI-NSPIRE Clocks
4 - compatible: Valid compatible properties include:
5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
7 "lsi,nspire-cx-clock" for the base clock in the CX model
8 "lsi,nspire-classic-clock" for the base clock in the older model
10 - reg: Physical base address of the controller and length of memory mapped
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
15 clock where it divides the rate from.
20 #clock-cells = <0>;
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| /linux/Documentation/devicetree/bindings/clock/ti/ |
| H A D | ti,divider-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments divider clock
10 - Tero Kristo <kristo@kernel.org>
13 This clock It assumes a register-mapped adjustable clock rate divider
14 that does not gate and has only one input clock or parent. By default the
25 ti,index-starts-at-one - valid divisor values start at 1, not the default
32 ti,index-power-of-two - valid divisor values are powers of two. E.g:
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| /linux/drivers/clk/ |
| H A D | clk-divider.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
7 * Adjustable divider clock implementation
10 #include <linux/clk-provider.h>
20 * DOC: basic adjustable divider clock that cannot gate
22 * Traits of this clock:
23 * prepare - clk_prepare only ensures that parents are prepared
24 * enable - clk_enable only ensures that parents are enabled
25 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
26 * parent - fixed parent. No clk_set_parent support
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| H A D | clk-xgene.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-xgene.c - AppliedMicro X-Gene Clock Interface
13 #include <linux/clk-provider.h>
41 /* PLL Clock */
63 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled()
81 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
83 if (pllclk->version <= 1) { in xgene_clk_pll_recalc_rate()
84 if (pllclk->type == PLL_TYPE_PCP) { in xgene_clk_pll_recalc_rate()
86 * PLL VCO = Reference clock * NF in xgene_clk_pll_recalc_rate()
93 * Fref = Reference Clock / NREF; in xgene_clk_pll_recalc_rate()
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| /linux/drivers/clk/ti/ |
| H A D | divider.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI Divider Clock
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
16 #include "clock.h"
26 for (clkt = table; clkt->div; clkt++) in _get_table_div()
27 if (clkt->val == val) in _get_table_div()
28 return clkt->div; in _get_table_div()
32 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument
38 if (divider->table) { in _setup_mask()
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| /linux/drivers/clk/tegra/ |
| H A D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
98 * @reg: register containing divider
99 * @flags: hardware-specific flags
100 * @shift: shift to the divider bit field
101 * @width: width of the divider bit field
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| /linux/drivers/clk/ingenic/ |
| H A D | cgu.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
27 * @n_shift: the number of bits to shift the divider value by (ie. the
28 * index of the lowest bit of the divider value in the PLL's
30 * @n_bits: the size of the divider field in bits
31 * @n_offset: the divider value which encodes to 0 in the PLL's control
33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34 * the index of the lowest bit of the post-VCO divider value in
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| /linux/drivers/clk/sophgo/ |
| H A D | clk-sg2042-clkgen.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Sophgo SG2042 Clock Generator Driver
12 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
19 #include "clk-sg2042.h"
23 #define R_PLL_STAT (0xC0 - R_PLL_BEGIN)
24 #define R_PLL_CLKEN_CONTROL (0xC4 - R_PLL_BEGIN)
25 #define R_MPLL_CONTROL (0xE8 - R_PLL_BEGIN)
26 #define R_FPLL_CONTROL (0xF4 - R_PLL_BEGIN)
27 #define R_DPLL0_CONTROL (0xF8 - R_PLL_BEGIN)
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| /linux/drivers/clk/bcm/ |
| H A D | clk-kona.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
20 /* The common clock framework uses u8 to represent a parent index */
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
42 /* Clock field state tests */
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| /linux/drivers/clk/renesas/ |
| H A D | rzv2h-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/V2H(P) Clock Pulse Generator
7 * Based on rzg2l-cpg.c
16 #include <linux/clk-provider.h>
26 #include <linux/reset-controller.h>
28 #include <dt-bindings/clock/renesas-cpg-mssr.h>
30 #include "rzv2h-cpg.h"
56 * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
65 * @num_resets: Number of Module Resets in info->resets[]
66 * @last_dt_core_clk: ID of the last Core Clock exported to DT
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| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap54xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
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| H A D | omap44xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP4 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
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| H A D | dm816x-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
5 #clock-cells = <1>;
6 compatible = "ti,dm816-fapll-clock";
9 clock-indices = <1>, <2>, <3>, <4>, <5>,
11 clock-output-names = "main_pll_clk1",
21 #clock-cells = <1>;
22 compatible = "ti,dm816-fapll-clock";
25 clock-indices = <1>, <2>, <3>, <4>;
26 clock-output-names = "ddr_pll_clk1",
33 #clock-cells = <1>;
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| /linux/include/linux/ |
| H A D | clk-provider.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
42 * struct clk_rate_request - Structure encoding the clk constraints that
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| /linux/drivers/clk/davinci/ |
| H A D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PLL clock driver for TI Davinci SoCs
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
12 #include <linux/clk-provider.h>
22 #include <linux/platform_data/clk-davinci-pll.h>
79 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
86 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
90 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
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| /linux/drivers/clk/samsung/ |
| H A D | clk-cpu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * This file contains the utility function to register CPU clock for Samsung
10 * Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a
11 * group of CPUs. The CPU clock is typically derived from a hierarchy of clock
12 * blocks which includes mux and divider blocks. There are a number of other
14 * clock for CPU domain. The rates of these auxiliary clocks are related to the
15 * CPU clock rate and this relation is usually specified in the hardware manual
18 * The below implementation of the CPU clock allows the rate changes of the CPU
19 * clock and the corresponding rate changes of the auxiliary clocks of the CPU
20 * domain. The platform clock driver provides a clock register configuration
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| /linux/drivers/clk/analogbits/ |
| H A D | wrpll-cln28hpc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
13 * The bulk of this code is primarily useful for clock configurations
14 * that must operate at arbitrary rates, as opposed to clock configurations
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
33 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
35 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
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| /linux/drivers/media/i2c/ |
| H A D | ccs-pll.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * drivers/media/i2c/ccs-pll.h
17 /* CSI-2 or CCP-2 */
22 /* op pix clock is for all lanes in total normally */
37 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39 * A single branch front-end of the CCS PLL tree.
41 * @pre_pll_clk_div: Pre-PLL clock divisor
43 * @pll_ip_clk_freq_hz: PLL input clock frequency
44 * @pll_op_clk_freq_hz: PLL output clock frequency
54 * struct ccs_pll_branch_bk - CCS PLL configuration (back)
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