Lines Matching +full:divider +full:- +full:clock

1 PLL divider based Dove clocks
9 ID	Clock
10 -------------
11 0	AXI bus clock
12 1	GPU clock
13 2	VMeta clock
14 3	LCD clock
17 - compatible : shall be "marvell,dove-divider-clock"
18 - reg : shall be the register address of the Core PLL and Clock Divider
20    Core PLL and Clock Divider Control 1 register.  Thus, it will have
22 - #clock-cells : from common clock binding; shall be set to 1
24 divider_clk: core-clock@64 {
25 	compatible = "marvell,dove-divider-clock";
27 	#clock-cells = <1>;