Lines Matching +full:divider +full:- +full:clock
1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
98 * @reg: register containing divider
99 * @flags: hardware-specific flags
100 * @shift: shift to the divider bit field
101 * @width: width of the divider bit field
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
108 * flag indicates that this divider is for fixed rate PLL.
109 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
110 * fraction bit is set. This flags indicates to calculate divider for which
112 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
113 * set when divider value is not 0. This flags indicates that the divider
154 * struct tegra_clk_pll_freq_table - PLL frequecy table
158 * @n: feedback divider
159 * @m: input divider
160 * @p: post divider
162 * @sdm_data: fraction divider setting (0 = disabled)
175 * struct pdiv_map - map post divider to hw value
177 * @pdiv: post divider
186 * struct div_nmp - offset and width of m,n and p fields
188 * @divn_shift: shift to the feedback divider bit field
189 * @divn_width: width of the feedback divider bit field
190 * @divm_shift: shift to the input divider bit field
191 * @divm_width: width of the input divider bit field
192 * @divp_shift: shift to the post divider bit field
193 * @divp_width: width of the post divider bit field
194 * @override_divn_shift: shift to the feedback divider bitfield in override reg
195 * @override_divm_shift: shift to the input divider bitfield in override reg
196 * @override_divp_shift: shift to the post divider bitfield in override reg
215 * struct tegra_clk_pll_params - PLL parameters
233 * @sdm_din_mask: Mask of SDM divider bits
241 * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM)
242 * @pmc_divp_reg: p divider PMC override register offset (PLLM)
247 * @max_p: maximum value for the p divider
249 * @pdiv_tohw: mapping of p divider to register values
256 * PLL's based on fractional divider value.
260 * divider range (if SDM is present)
275 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
277 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
279 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
281 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
283 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
284 * that it is PLLU and invert post divider value.
285 * TEGRA_PLLM - PLLM has additional override settings in PMC. This
287 * TEGRA_PLL_FIXED - We are not supposed to change output frequency
289 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
290 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
292 * TEGRA_PLL_BYPASS - PLL has bypass bit
293 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
294 * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
296 * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This
298 * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output
369 * struct tegra_clk_pll - Tegra PLL clock
371 * @hw: handle between common and hardware-specifix interfaces
388 * struct tegra_audio_clk_info - Tegra Audio Clk Information
497 * struct tegra_clk_pll_out - PLL divider down clock
499 * @hw: handle between common and hardware-specific interfaces
500 * @reg: register containing the PLL divider
501 * @enb_bit_idx: bit to enable/disable PLL divider
502 * @rst_bit_idx: bit to reset PLL divider
504 * @flags: hardware-specific flags
524 * struct tegra_clk_periph_regs - Registers controlling peripheral clock
527 * @enb_set_reg: write 1 to enable clock
528 * @enb_clr_reg: write 1 to disable clock
543 * struct tegra_clk_periph_gate - peripheral gate clock
546 * @hw: handle between common and hardware-specific interfaces
549 * @flags: hardware-specific flags
550 * @clk_num: Clock number
551 * @enable_refcnt: array to maintain reference count of the clock
554 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
556 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
559 * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
605 * struct clk-periph - peripheral clock
608 * @hw: handle between common and hardware-specific interfaces
609 * @mux: mux clock
610 * @divider: divider clock
611 * @gate: gate clock
612 * @mux_ops: mux clock ops
613 * @div_ops: divider clock ops
614 * @gate_ops: gate clock ops
620 struct tegra_clk_frac_div divider; member
654 .divider = { \
711 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
720 * struct clk_super_mux - super clock
722 * @hw: handle between common and hardware-specific interfaces
725 * @flags: hardware-specific flags
726 * @div2_index: bit controlling divide-by-2
731 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
732 * that this is LP cluster clock.
733 * TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5
735 * to configure additional bit PLLP_OUT_CPU in the clock registers.
736 * TEGRA20_SUPER_CLK - Tegra20 doesn't have a dedicated divider for Super
737 * clocks, it only has a clock-skipper.
774 * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
776 * @hw: handle between common and hardware-specific interfaces
777 * @reg: register controlling mux and divider
778 * @flags: hardware-specific flags
780 * @gate: gate clock
781 * @gate_ops: gate clock ops
799 * struct clk_init_table - clock initialization table
800 * @clk_id: clock id as mentioned in device tree bindings
801 * @parent_id: parent clock id as mentioned in device tree bindings
813 * struct clk_duplicate - duplicate clocks
814 * @clk_id: clock id as mentioned in device tree bindings
815 * @lookup: duplicate lookup entry for the clock