Lines Matching +full:divider +full:- +full:clock

1 /* SPDX-License-Identifier: GPL-2.0 */
8  * @defgroup clock_ids Clock Identifiers
235  *   @defgroup nafll_clks NAFLL clock sources
355  * pwrclk. @warning: This is almost certainly not the clock you think
356  * it is. If you're looking for the clock of the graphics engine, see
362 /** @brief output of the divider IPFS_CLK_DIVISOR */
417  * @brief controls the EMC clock frequency.
418  * @details Doing a clk_set_rate on this clock will select the
419  * appropriate clock source, program the source rate and execute a
420  * specific sequence to switch to the new clock source for both memory
551 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
555 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
563 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */
565 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
567 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
677 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read…
693 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */
697 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */
699 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */
701 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */
711 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
741 /** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 out…
742   *      * VCO/pdiv defined by this clock object
747 /** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */
749 /** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */
753 /** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider …
755 /** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
757 /** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
759 /** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is T…
761 /** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
763 /** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
767 /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_…
769 /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_…
771 /** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */
773 /** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */
775 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */
779 /** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE vol…
783  * @details This clock only has enable and disable methods. When the
791 /** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
797 /** @brief fixed /5 divider.  Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used a…
801 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */
803 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */
815 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
818  * @brief GPC2CLK-div-2
819  * @details fixed /2 divider. Output frequency is
820  * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the
823 /** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */
825 /** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
841  * @details Note that this clock only controls the VCO output, before
842  * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
850 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
868 /** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */
870 /** @brief NAFLL clock source for AXI_CBB */
872 /** @brief NAFLL clock source for BPMP */
874 /** @brief NAFLL clock source for ISP */
876 /** @brief NAFLL clock source for NVDEC */
878 /** @brief NAFLL clock source for NVENC */
880 /** @brief NAFLL clock source for NVJPG */
882 /** @brief NAFLL clock source for SCE */
884 /** @brief NAFLL clock source for SE */
886 /** @brief NAFLL clock source for TSEC */
888 /** @brief NAFLL clock source for TSECB */
890 /** @brief NAFLL clock source for VI */
892 /** @brief NAFLL clock source for VIC */
894 /** @brief NAFLL clock source for DISP */
896 /** @brief NAFLL clock source for GPU */
898 /** @brief NAFLL clock source for M-CPU cluster */
900 /** @brief NAFLL clock source for B-CPU cluster */
904 /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
906 /** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */
910 /** @brief clock recovered from EAVB input */
912 /** @brief clock recovered from DTV input */
918 /** @brief clock recovered from I2S1 input */
920 /** @brief clock recovered from I2S2 input */
922 /** @brief clock recovered from I2S3 input */
924 /** @brief clock recovered from I2S4 input */
926 /** @brief clock recovered from I2S5 input */
928 /** @brief clock recovered from I2S6 input */
930 /** @brief clock recovered from SPDIFIN input */
935  * @details maximum clock identifier value plus one.