Lines Matching +full:divider +full:- +full:clock

2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
7 This binding uses the common clock binding[1].
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
14 - clocks : parent clock phandle
15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 		post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
23 		#clock-cells = <0>;
24 		compatible = "ti,keystone,main-pll-clock";
27 		reg-names = "control", "multiplier", "post-divider";
28 		fixed-postdiv = <2>;
32 		#clock-cells = <0>;
33 		compatible = "ti,keystone,pll-clock";
35 		clock-output-names = "pa-pll-clk";
37 		reg-names = "control";
41 - #clock-cells : from common clock binding; shall be set to 0.
42 - compatible : shall be "ti,keystone,pll-mux-clock"
43 - clocks : link phandles of parent clocks
44 - reg - pll mux register
45 - bit-shift : number of bits to shift the bit-mask
46 - bit-mask : arbitrary bitmask for programming the mux
49 - clock-output-names : From common clock binding.
53 		#clock-cells = <0>;
54 		compatible = "ti,keystone,pll-mux-clock";
57 		bit-shift = <23>;
58 		bit-mask = <1>;
59 		clock-output-names = "mainmuxclk";
63 - #clock-cells : from common clock binding; shall be set to 0.
64 - compatible : shall be "ti,keystone,pll-divider-clock"
65 - clocks : parent clock phandle
66 - reg - pll mux register
67 - bit-shift : number of bits to shift the bit-mask
68 - bit-mask : arbitrary bitmask for programming the divider
71 - clock-output-names : From common clock binding.
75 		#clock-cells = <0>;
76 		compatible = "ti,keystone,pll-divider-clock";
79 		bit-shift = <0>;
80 		bit-mask = <8>;
81 		clock-output-names = "gemtraceclk";