1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Texas Instruments divider clock 8 9maintainers: 10 - Tero Kristo <kristo@kernel.org> 11 12description: | 13 This clock It assumes a register-mapped adjustable clock rate divider 14 that does not gate and has only one input clock or parent. By default the 15 value programmed into the register is one less than the actual divisor value. 16 E.g: 17 18 register value actual divisor value 19 0 1 20 1 2 21 2 3 22 23 This assumption may be modified by the following optional properties: 24 25 ti,index-starts-at-one - valid divisor values start at 1, not the default 26 of 0. E.g: 27 register value actual divisor value 28 1 1 29 2 2 30 3 3 31 32 ti,index-power-of-two - valid divisor values are powers of two. E.g: 33 register value actual divisor value 34 0 1 35 1 2 36 2 4 37 38 Additionally an array of valid dividers may be supplied like so: 39 40 ti,dividers = <4>, <8>, <0>, <16>; 41 42 Which will map the resulting values to a divisor table by their index: 43 register value actual divisor value 44 0 4 45 1 8 46 2 <invalid divisor, skipped> 47 3 16 48 49 Any zero value in this array means the corresponding bit-value is invalid 50 and must not be used. 51 52 The binding must also provide the register to control the divider and 53 unless the divider array is provided, min and max dividers. Optionally 54 the number of bits to shift that mask, if necessary. If the shift value 55 is missing it is the same as supplying a zero shift. 56 57 This binding can also optionally provide support to the hardware autoidle 58 feature, see [1]. 59 60 [1] Documentation/devicetree/bindings/clock/ti/autoidle.txt 61 62properties: 63 compatible: 64 enum: 65 - ti,divider-clock 66 - ti,composite-divider-clock 67 68 "#clock-cells": 69 const: 0 70 71 clocks: 72 maxItems: 1 73 74 clock-output-names: 75 maxItems: 1 76 77 reg: 78 maxItems: 1 79 80 ti,dividers: 81 $ref: /schemas/types.yaml#/definitions/uint32-array 82 description: 83 array of integers defining divisors 84 85 ti,bit-shift: 86 $ref: /schemas/types.yaml#/definitions/uint32 87 description: 88 number of bits to shift the divider value 89 maximum: 31 90 default: 0 91 92 ti,min-div: 93 $ref: /schemas/types.yaml#/definitions/uint32 94 description: 95 min divisor for dividing the input clock rate, only 96 needed if the first divisor is offset from the default value (1) 97 minimum: 1 98 default: 1 99 100 101 ti,max-div: 102 $ref: /schemas/types.yaml#/definitions/uint32 103 description: 104 max divisor for dividing the input clock rate, only needed 105 if ti,dividers is not defined. 106 107 ti,index-starts-at-one: 108 type: boolean 109 description: 110 valid divisor programming starts at 1, not zero, 111 only valid if ti,dividers is not defined 112 113 ti,index-power-of-two: 114 type: boolean 115 description: 116 valid divisor programming must be a power of two, 117 only valid if ti,dividers is not defined. 118 119 ti,autoidle-shift: 120 $ref: /schemas/types.yaml#/definitions/uint32 121 description: 122 bit shift of the autoidle enable bit for the clock, 123 see [1]. 124 maximum: 31 125 default: 0 126 127 ti,invert-autoidle-bit: 128 type: boolean 129 description: 130 autoidle is enabled by setting the bit to 0, 131 see [1] 132 133 ti,set-rate-parent: 134 type: boolean 135 description: 136 clk_set_rate is propagated to parent | 137 138 ti,latch-bit: 139 $ref: /schemas/types.yaml#/definitions/uint32 140 description: 141 latch the divider value to HW, only needed if the register 142 compatible access requires this. As an example dra76x DPLL_GMAC 143 H14 divider implements such behavior. 144 145dependentSchemas: 146 ti,dividers: 147 properties: 148 ti,min-div: false 149 ti,max-div: false 150 ti,index-power-of-two: false 151 ti,index-starts-at-one: false 152 153required: 154 - compatible 155 - "#clock-cells" 156 - clocks 157 - reg 158 159additionalProperties: false 160 161examples: 162 - | 163 bus { 164 #address-cells = <1>; 165 #size-cells = <0>; 166 167 clock-controller@190 { 168 #clock-cells = <0>; 169 compatible = "ti,divider-clock"; 170 clocks = <&dpll_usb_ck>; 171 ti,max-div = <127>; 172 reg = <0x190>; 173 ti,index-starts-at-one; 174 }; 175 176 clock-controller@528 { 177 #clock-cells = <0>; 178 compatible = "ti,divider-clock"; 179 clocks = <&abe_clk>; 180 ti,bit-shift = <24>; 181 reg = <0x528>; 182 ti,max-div = <2>; 183 }; 184 185 clock-controller@a40 { 186 #clock-cells = <0>; 187 compatible = "ti,composite-divider-clock"; 188 clocks = <&corex2_fck>; 189 ti,bit-shift = <8>; 190 reg = <0x0a40>; 191 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; 192 }; 193 }; 194