1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2ddeac8d9SThomas Abraham /*
3ddeac8d9SThomas Abraham * Copyright (c) 2014 Samsung Electronics Co., Ltd.
4ddeac8d9SThomas Abraham * Author: Thomas Abraham <thomas.ab@samsung.com>
5ddeac8d9SThomas Abraham *
6ddeac8d9SThomas Abraham * Copyright (c) 2015 Samsung Electronics Co., Ltd.
7ddeac8d9SThomas Abraham * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
8ddeac8d9SThomas Abraham *
9ddeac8d9SThomas Abraham * This file contains the utility function to register CPU clock for Samsung
10ddeac8d9SThomas Abraham * Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a
11ddeac8d9SThomas Abraham * group of CPUs. The CPU clock is typically derived from a hierarchy of clock
12ddeac8d9SThomas Abraham * blocks which includes mux and divider blocks. There are a number of other
13ddeac8d9SThomas Abraham * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
14ddeac8d9SThomas Abraham * clock for CPU domain. The rates of these auxiliary clocks are related to the
15ddeac8d9SThomas Abraham * CPU clock rate and this relation is usually specified in the hardware manual
16ddeac8d9SThomas Abraham * of the SoC or supplied after the SoC characterization.
17ddeac8d9SThomas Abraham *
18ddeac8d9SThomas Abraham * The below implementation of the CPU clock allows the rate changes of the CPU
19f707e891SSam Protsenko * clock and the corresponding rate changes of the auxiliary clocks of the CPU
20ddeac8d9SThomas Abraham * domain. The platform clock driver provides a clock register configuration
21ddeac8d9SThomas Abraham * for each configurable rate which is then used to program the clock hardware
22f707e891SSam Protsenko * registers to achieve a fast coordinated rate change for all the CPU domain
23ddeac8d9SThomas Abraham * clocks.
24ddeac8d9SThomas Abraham *
25ddeac8d9SThomas Abraham * On a rate change request for the CPU clock, the rate change is propagated
26ddeac8d9SThomas Abraham * up to the PLL supplying the clock to the CPU domain clock blocks. While the
27ddeac8d9SThomas Abraham * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
28ddeac8d9SThomas Abraham * alternate clock source. If required, the alternate clock source is divided
29ddeac8d9SThomas Abraham * down in order to keep the output clock rate within the previous OPP limits.
30ddeac8d9SThomas Abraham */
31ddeac8d9SThomas Abraham
3261f4399cSSam Protsenko #include <linux/delay.h>
33ddeac8d9SThomas Abraham #include <linux/errno.h>
3462e59c4eSStephen Boyd #include <linux/io.h>
356f1ed07aSStephen Boyd #include <linux/slab.h>
366f1ed07aSStephen Boyd #include <linux/clk.h>
376f1ed07aSStephen Boyd #include <linux/clk-provider.h>
38a36bda74SSam Protsenko
39a36bda74SSam Protsenko #include "clk.h"
40ddeac8d9SThomas Abraham #include "clk-cpu.h"
41ddeac8d9SThomas Abraham
42c9bc1f77SSam Protsenko struct exynos_cpuclk;
43c9bc1f77SSam Protsenko
44c9bc1f77SSam Protsenko typedef int (*exynos_rate_change_fn_t)(struct clk_notifier_data *ndata,
45c9bc1f77SSam Protsenko struct exynos_cpuclk *cpuclk);
46c9bc1f77SSam Protsenko
47a36bda74SSam Protsenko /**
4878bc2312SSam Protsenko * struct exynos_cpuclk_regs - Register offsets for CPU related clocks
4978bc2312SSam Protsenko * @mux_sel: offset of CPU MUX_SEL register (for selecting MUX clock parent)
5078bc2312SSam Protsenko * @mux_stat: offset of CPU MUX_STAT register (for checking MUX clock status)
5178bc2312SSam Protsenko * @div_cpu0: offset of CPU DIV0 register (for modifying divider values)
5278bc2312SSam Protsenko * @div_cpu1: offset of CPU DIV1 register (for modifying divider values)
5378bc2312SSam Protsenko * @div_stat_cpu0: offset of CPU DIV0_STAT register (for checking DIV status)
5478bc2312SSam Protsenko * @div_stat_cpu1: offset of CPU DIV1_STAT register (for checking DIV status)
5561f4399cSSam Protsenko * @mux: offset of MUX register for choosing CPU clock source
5661f4399cSSam Protsenko * @divs: offsets of DIV registers (ACLK, ATCLK, PCLKDBG and PERIPHCLK)
5778bc2312SSam Protsenko */
5878bc2312SSam Protsenko struct exynos_cpuclk_regs {
5978bc2312SSam Protsenko u32 mux_sel;
6078bc2312SSam Protsenko u32 mux_stat;
6178bc2312SSam Protsenko u32 div_cpu0;
6278bc2312SSam Protsenko u32 div_cpu1;
6378bc2312SSam Protsenko u32 div_stat_cpu0;
6478bc2312SSam Protsenko u32 div_stat_cpu1;
6561f4399cSSam Protsenko
6661f4399cSSam Protsenko u32 mux;
6761f4399cSSam Protsenko u32 divs[4];
6878bc2312SSam Protsenko };
6978bc2312SSam Protsenko
7078bc2312SSam Protsenko /**
719c746e5aSSam Protsenko * struct exynos_cpuclk_chip - Chip specific data for CPU clock
7278bc2312SSam Protsenko * @regs: register offsets for CPU related clocks
739c746e5aSSam Protsenko * @pre_rate_cb: callback to run before CPU clock rate change
749c746e5aSSam Protsenko * @post_rate_cb: callback to run after CPU clock rate change
759c746e5aSSam Protsenko */
769c746e5aSSam Protsenko struct exynos_cpuclk_chip {
7778bc2312SSam Protsenko const struct exynos_cpuclk_regs *regs;
789c746e5aSSam Protsenko exynos_rate_change_fn_t pre_rate_cb;
799c746e5aSSam Protsenko exynos_rate_change_fn_t post_rate_cb;
809c746e5aSSam Protsenko };
819c746e5aSSam Protsenko
829c746e5aSSam Protsenko /**
83a36bda74SSam Protsenko * struct exynos_cpuclk - information about clock supplied to a CPU core
84a36bda74SSam Protsenko * @hw: handle between CCF and CPU clock
85a36bda74SSam Protsenko * @alt_parent: alternate parent clock to use when switching the speed
86a36bda74SSam Protsenko * of the primary parent clock
87338f1c25SSam Protsenko * @base: start address of the CPU clock registers block
88a36bda74SSam Protsenko * @lock: cpu clock domain register access lock
89a36bda74SSam Protsenko * @cfg: cpu clock rate configuration data
90a36bda74SSam Protsenko * @num_cfgs: number of array elements in @cfg array
91a36bda74SSam Protsenko * @clk_nb: clock notifier registered for changes in clock speed of the
92a36bda74SSam Protsenko * primary parent clock
93a36bda74SSam Protsenko * @flags: configuration flags for the CPU clock
949c746e5aSSam Protsenko * @chip: chip-specific data for the CPU clock
95a36bda74SSam Protsenko *
96a36bda74SSam Protsenko * This structure holds information required for programming the CPU clock for
97a36bda74SSam Protsenko * various clock speeds.
98a36bda74SSam Protsenko */
99a36bda74SSam Protsenko struct exynos_cpuclk {
100a36bda74SSam Protsenko struct clk_hw hw;
101a36bda74SSam Protsenko const struct clk_hw *alt_parent;
102338f1c25SSam Protsenko void __iomem *base;
103a36bda74SSam Protsenko spinlock_t *lock;
104a36bda74SSam Protsenko const struct exynos_cpuclk_cfg_data *cfg;
105a36bda74SSam Protsenko const unsigned long num_cfgs;
106a36bda74SSam Protsenko struct notifier_block clk_nb;
107a36bda74SSam Protsenko unsigned long flags;
1089c746e5aSSam Protsenko const struct exynos_cpuclk_chip *chip;
109a36bda74SSam Protsenko };
110a36bda74SSam Protsenko
111be20ccc1SSam Protsenko /* ---- Common code --------------------------------------------------------- */
112be20ccc1SSam Protsenko
113be20ccc1SSam Protsenko /* Divider stabilization time, msec */
114be20ccc1SSam Protsenko #define MAX_STAB_TIME 10
115be20ccc1SSam Protsenko #define MAX_DIV 8
116be20ccc1SSam Protsenko #define DIV_MASK GENMASK(2, 0)
117be20ccc1SSam Protsenko #define DIV_MASK_ALL GENMASK(31, 0)
118be20ccc1SSam Protsenko #define MUX_MASK GENMASK(2, 0)
119be20ccc1SSam Protsenko
120ddeac8d9SThomas Abraham /*
121ddeac8d9SThomas Abraham * Helper function to wait until divider(s) have stabilized after the divider
122ddeac8d9SThomas Abraham * value has changed.
123ddeac8d9SThomas Abraham */
wait_until_divider_stable(void __iomem * div_reg,unsigned long mask)124ddeac8d9SThomas Abraham static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask)
125ddeac8d9SThomas Abraham {
126f707e891SSam Protsenko unsigned long timeout = jiffies + msecs_to_jiffies(MAX_STAB_TIME);
127ddeac8d9SThomas Abraham
128ddeac8d9SThomas Abraham do {
129ddeac8d9SThomas Abraham if (!(readl(div_reg) & mask))
130ddeac8d9SThomas Abraham return;
131ddeac8d9SThomas Abraham } while (time_before(jiffies, timeout));
132ddeac8d9SThomas Abraham
133ddeac8d9SThomas Abraham if (!(readl(div_reg) & mask))
134ddeac8d9SThomas Abraham return;
135ddeac8d9SThomas Abraham
136ddeac8d9SThomas Abraham pr_err("%s: timeout in divider stablization\n", __func__);
137ddeac8d9SThomas Abraham }
138ddeac8d9SThomas Abraham
139ddeac8d9SThomas Abraham /*
140ddeac8d9SThomas Abraham * Helper function to wait until mux has stabilized after the mux selection
141ddeac8d9SThomas Abraham * value was changed.
142ddeac8d9SThomas Abraham */
wait_until_mux_stable(void __iomem * mux_reg,u32 mux_pos,unsigned long mask,unsigned long mux_value)143ddeac8d9SThomas Abraham static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
144152cc747SSam Protsenko unsigned long mask, unsigned long mux_value)
145ddeac8d9SThomas Abraham {
146f707e891SSam Protsenko unsigned long timeout = jiffies + msecs_to_jiffies(MAX_STAB_TIME);
147ddeac8d9SThomas Abraham
148ddeac8d9SThomas Abraham do {
149152cc747SSam Protsenko if (((readl(mux_reg) >> mux_pos) & mask) == mux_value)
150ddeac8d9SThomas Abraham return;
151ddeac8d9SThomas Abraham } while (time_before(jiffies, timeout));
152ddeac8d9SThomas Abraham
153152cc747SSam Protsenko if (((readl(mux_reg) >> mux_pos) & mask) == mux_value)
154ddeac8d9SThomas Abraham return;
155ddeac8d9SThomas Abraham
156ddeac8d9SThomas Abraham pr_err("%s: re-parenting mux timed-out\n", __func__);
157ddeac8d9SThomas Abraham }
158ddeac8d9SThomas Abraham
15978bc2312SSam Protsenko /*
16078bc2312SSam Protsenko * Helper function to set the 'safe' dividers for the CPU clock. The parameters
16178bc2312SSam Protsenko * div and mask contain the divider value and the register bit mask of the
16278bc2312SSam Protsenko * dividers to be programmed.
16378bc2312SSam Protsenko */
exynos_set_safe_div(struct exynos_cpuclk * cpuclk,unsigned long div,unsigned long mask)16478bc2312SSam Protsenko static void exynos_set_safe_div(struct exynos_cpuclk *cpuclk, unsigned long div,
16578bc2312SSam Protsenko unsigned long mask)
16678bc2312SSam Protsenko {
16778bc2312SSam Protsenko const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
16878bc2312SSam Protsenko void __iomem *base = cpuclk->base;
16978bc2312SSam Protsenko unsigned long div0;
170ddeac8d9SThomas Abraham
17178bc2312SSam Protsenko div0 = readl(base + regs->div_cpu0);
17278bc2312SSam Protsenko div0 = (div0 & ~mask) | (div & mask);
17378bc2312SSam Protsenko writel(div0, base + regs->div_cpu0);
17478bc2312SSam Protsenko wait_until_divider_stable(base + regs->div_stat_cpu0, mask);
17578bc2312SSam Protsenko }
17678bc2312SSam Protsenko
17778bc2312SSam Protsenko /* ---- Exynos 3/4/5 -------------------------------------------------------- */
178ddeac8d9SThomas Abraham
179be20ccc1SSam Protsenko #define E4210_DIV0_RATIO0_MASK GENMASK(2, 0)
180be20ccc1SSam Protsenko #define E4210_DIV1_HPM_MASK GENMASK(6, 4)
181be20ccc1SSam Protsenko #define E4210_DIV1_COPY_MASK GENMASK(2, 0)
182be20ccc1SSam Protsenko #define E4210_MUX_HPM_MASK BIT(20)
183be20ccc1SSam Protsenko #define E4210_DIV0_ATB_SHIFT 16
184be20ccc1SSam Protsenko #define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT)
185ddeac8d9SThomas Abraham
18678bc2312SSam Protsenko static const struct exynos_cpuclk_regs e4210_cpuclk_regs = {
18778bc2312SSam Protsenko .mux_sel = 0x200,
18878bc2312SSam Protsenko .mux_stat = 0x400,
18978bc2312SSam Protsenko .div_cpu0 = 0x500,
19078bc2312SSam Protsenko .div_cpu1 = 0x504,
19178bc2312SSam Protsenko .div_stat_cpu0 = 0x600,
19278bc2312SSam Protsenko .div_stat_cpu1 = 0x604,
19378bc2312SSam Protsenko };
194ddeac8d9SThomas Abraham
195ddeac8d9SThomas Abraham /* handler for pre-rate change notification from parent clock */
exynos_cpuclk_pre_rate_change(struct clk_notifier_data * ndata,struct exynos_cpuclk * cpuclk)196ddeac8d9SThomas Abraham static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
197c9bc1f77SSam Protsenko struct exynos_cpuclk *cpuclk)
198ddeac8d9SThomas Abraham {
199ddeac8d9SThomas Abraham const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
20078bc2312SSam Protsenko const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
201338f1c25SSam Protsenko void __iomem *base = cpuclk->base;
2021da220e3SMarek Szyprowski unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
203ddeac8d9SThomas Abraham unsigned long div0, div1 = 0, mux_reg;
2046b4feaeaSMarek Szyprowski unsigned long flags;
205ddeac8d9SThomas Abraham
206ddeac8d9SThomas Abraham /* find out the divider values to use for clock data */
207ddeac8d9SThomas Abraham while ((cfg_data->prate * 1000) != ndata->new_rate) {
208ddeac8d9SThomas Abraham if (cfg_data->prate == 0)
209ddeac8d9SThomas Abraham return -EINVAL;
210ddeac8d9SThomas Abraham cfg_data++;
211ddeac8d9SThomas Abraham }
212ddeac8d9SThomas Abraham
2136b4feaeaSMarek Szyprowski spin_lock_irqsave(cpuclk->lock, flags);
214ddeac8d9SThomas Abraham
215ddeac8d9SThomas Abraham /*
216ddeac8d9SThomas Abraham * For the selected PLL clock frequency, get the pre-defined divider
217ddeac8d9SThomas Abraham * values. If the clock for sclk_hpm is not sourced from apll, then
218ddeac8d9SThomas Abraham * the values for DIV_COPY and DIV_HPM dividers need not be set.
219ddeac8d9SThomas Abraham */
220ddeac8d9SThomas Abraham div0 = cfg_data->div0;
2219e294bf8SBartlomiej Zolnierkiewicz if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
222ddeac8d9SThomas Abraham div1 = cfg_data->div1;
22378bc2312SSam Protsenko if (readl(base + regs->mux_sel) & E4210_MUX_HPM_MASK)
22478bc2312SSam Protsenko div1 = readl(base + regs->div_cpu1) &
225ddeac8d9SThomas Abraham (E4210_DIV1_HPM_MASK | E4210_DIV1_COPY_MASK);
226ddeac8d9SThomas Abraham }
227ddeac8d9SThomas Abraham
228ddeac8d9SThomas Abraham /*
229ddeac8d9SThomas Abraham * If the old parent clock speed is less than the clock speed of
230ddeac8d9SThomas Abraham * the alternate parent, then it should be ensured that at no point
231ddeac8d9SThomas Abraham * the armclk speed is more than the old_prate until the dividers are
232ddeac8d9SThomas Abraham * set. Also workaround the issue of the dividers being set to lower
233ddeac8d9SThomas Abraham * values before the parent clock speed is set to new lower speed
234ddeac8d9SThomas Abraham * (this can result in too high speed of armclk output clocks).
235ddeac8d9SThomas Abraham */
236ddeac8d9SThomas Abraham if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
237ddeac8d9SThomas Abraham unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
238f707e891SSam Protsenko unsigned long alt_div, alt_div_mask = DIV_MASK;
239ddeac8d9SThomas Abraham
240ddeac8d9SThomas Abraham alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
241ddeac8d9SThomas Abraham WARN_ON(alt_div >= MAX_DIV);
242ddeac8d9SThomas Abraham
2439e294bf8SBartlomiej Zolnierkiewicz if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
244ddeac8d9SThomas Abraham /*
245ddeac8d9SThomas Abraham * In Exynos4210, ATB clock parent is also mout_core. So
246ddeac8d9SThomas Abraham * ATB clock also needs to be mantained at safe speed.
247ddeac8d9SThomas Abraham */
248ddeac8d9SThomas Abraham alt_div |= E4210_DIV0_ATB_MASK;
249ddeac8d9SThomas Abraham alt_div_mask |= E4210_DIV0_ATB_MASK;
250ddeac8d9SThomas Abraham }
25178bc2312SSam Protsenko exynos_set_safe_div(cpuclk, alt_div, alt_div_mask);
252ddeac8d9SThomas Abraham div0 |= alt_div;
253ddeac8d9SThomas Abraham }
254ddeac8d9SThomas Abraham
255ddeac8d9SThomas Abraham /* select sclk_mpll as the alternate parent */
25678bc2312SSam Protsenko mux_reg = readl(base + regs->mux_sel);
25778bc2312SSam Protsenko writel(mux_reg | (1 << 16), base + regs->mux_sel);
258152cc747SSam Protsenko wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 2);
259ddeac8d9SThomas Abraham
260ddeac8d9SThomas Abraham /* alternate parent is active now. set the dividers */
26178bc2312SSam Protsenko writel(div0, base + regs->div_cpu0);
26278bc2312SSam Protsenko wait_until_divider_stable(base + regs->div_stat_cpu0, DIV_MASK_ALL);
263ddeac8d9SThomas Abraham
2649e294bf8SBartlomiej Zolnierkiewicz if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
26578bc2312SSam Protsenko writel(div1, base + regs->div_cpu1);
26678bc2312SSam Protsenko wait_until_divider_stable(base + regs->div_stat_cpu1,
267ddeac8d9SThomas Abraham DIV_MASK_ALL);
268ddeac8d9SThomas Abraham }
269ddeac8d9SThomas Abraham
2706b4feaeaSMarek Szyprowski spin_unlock_irqrestore(cpuclk->lock, flags);
271ddeac8d9SThomas Abraham return 0;
272ddeac8d9SThomas Abraham }
273ddeac8d9SThomas Abraham
274ddeac8d9SThomas Abraham /* handler for post-rate change notification from parent clock */
exynos_cpuclk_post_rate_change(struct clk_notifier_data * ndata,struct exynos_cpuclk * cpuclk)275ddeac8d9SThomas Abraham static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
276c9bc1f77SSam Protsenko struct exynos_cpuclk *cpuclk)
277ddeac8d9SThomas Abraham {
278ddeac8d9SThomas Abraham const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
27978bc2312SSam Protsenko const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
280338f1c25SSam Protsenko void __iomem *base = cpuclk->base;
281ddeac8d9SThomas Abraham unsigned long div = 0, div_mask = DIV_MASK;
282ddeac8d9SThomas Abraham unsigned long mux_reg;
2836b4feaeaSMarek Szyprowski unsigned long flags;
284ddeac8d9SThomas Abraham
285ddeac8d9SThomas Abraham /* find out the divider values to use for clock data */
2869e294bf8SBartlomiej Zolnierkiewicz if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
287ddeac8d9SThomas Abraham while ((cfg_data->prate * 1000) != ndata->new_rate) {
288ddeac8d9SThomas Abraham if (cfg_data->prate == 0)
289ddeac8d9SThomas Abraham return -EINVAL;
290ddeac8d9SThomas Abraham cfg_data++;
291ddeac8d9SThomas Abraham }
292ddeac8d9SThomas Abraham }
293ddeac8d9SThomas Abraham
2946b4feaeaSMarek Szyprowski spin_lock_irqsave(cpuclk->lock, flags);
295ddeac8d9SThomas Abraham
296ddeac8d9SThomas Abraham /* select mout_apll as the alternate parent */
29778bc2312SSam Protsenko mux_reg = readl(base + regs->mux_sel);
29878bc2312SSam Protsenko writel(mux_reg & ~(1 << 16), base + regs->mux_sel);
299152cc747SSam Protsenko wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 1);
300ddeac8d9SThomas Abraham
3019e294bf8SBartlomiej Zolnierkiewicz if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
302ddeac8d9SThomas Abraham div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
303ddeac8d9SThomas Abraham div_mask |= E4210_DIV0_ATB_MASK;
304ddeac8d9SThomas Abraham }
305ddeac8d9SThomas Abraham
30678bc2312SSam Protsenko exynos_set_safe_div(cpuclk, div, div_mask);
3076b4feaeaSMarek Szyprowski spin_unlock_irqrestore(cpuclk->lock, flags);
308ddeac8d9SThomas Abraham return 0;
309ddeac8d9SThomas Abraham }
310ddeac8d9SThomas Abraham
311be20ccc1SSam Protsenko /* ---- Exynos5433 ---------------------------------------------------------- */
312be20ccc1SSam Protsenko
31378bc2312SSam Protsenko static const struct exynos_cpuclk_regs e5433_cpuclk_regs = {
31478bc2312SSam Protsenko .mux_sel = 0x208,
31578bc2312SSam Protsenko .mux_stat = 0x408,
31678bc2312SSam Protsenko .div_cpu0 = 0x600,
31778bc2312SSam Protsenko .div_cpu1 = 0x604,
31878bc2312SSam Protsenko .div_stat_cpu0 = 0x700,
31978bc2312SSam Protsenko .div_stat_cpu1 = 0x704,
32078bc2312SSam Protsenko };
32153f69967SBartlomiej Zolnierkiewicz
32253f69967SBartlomiej Zolnierkiewicz /* handler for pre-rate change notification from parent clock */
exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data * ndata,struct exynos_cpuclk * cpuclk)32353f69967SBartlomiej Zolnierkiewicz static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
324c9bc1f77SSam Protsenko struct exynos_cpuclk *cpuclk)
32553f69967SBartlomiej Zolnierkiewicz {
32653f69967SBartlomiej Zolnierkiewicz const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
32778bc2312SSam Protsenko const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
328338f1c25SSam Protsenko void __iomem *base = cpuclk->base;
3291da220e3SMarek Szyprowski unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
33053f69967SBartlomiej Zolnierkiewicz unsigned long div0, div1 = 0, mux_reg;
33153f69967SBartlomiej Zolnierkiewicz unsigned long flags;
33253f69967SBartlomiej Zolnierkiewicz
33353f69967SBartlomiej Zolnierkiewicz /* find out the divider values to use for clock data */
33453f69967SBartlomiej Zolnierkiewicz while ((cfg_data->prate * 1000) != ndata->new_rate) {
33553f69967SBartlomiej Zolnierkiewicz if (cfg_data->prate == 0)
33653f69967SBartlomiej Zolnierkiewicz return -EINVAL;
33753f69967SBartlomiej Zolnierkiewicz cfg_data++;
33853f69967SBartlomiej Zolnierkiewicz }
33953f69967SBartlomiej Zolnierkiewicz
34053f69967SBartlomiej Zolnierkiewicz spin_lock_irqsave(cpuclk->lock, flags);
34153f69967SBartlomiej Zolnierkiewicz
34253f69967SBartlomiej Zolnierkiewicz /*
34353f69967SBartlomiej Zolnierkiewicz * For the selected PLL clock frequency, get the pre-defined divider
34453f69967SBartlomiej Zolnierkiewicz * values.
34553f69967SBartlomiej Zolnierkiewicz */
34653f69967SBartlomiej Zolnierkiewicz div0 = cfg_data->div0;
34753f69967SBartlomiej Zolnierkiewicz div1 = cfg_data->div1;
34853f69967SBartlomiej Zolnierkiewicz
34953f69967SBartlomiej Zolnierkiewicz /*
35053f69967SBartlomiej Zolnierkiewicz * If the old parent clock speed is less than the clock speed of
35153f69967SBartlomiej Zolnierkiewicz * the alternate parent, then it should be ensured that at no point
35253f69967SBartlomiej Zolnierkiewicz * the armclk speed is more than the old_prate until the dividers are
35353f69967SBartlomiej Zolnierkiewicz * set. Also workaround the issue of the dividers being set to lower
35453f69967SBartlomiej Zolnierkiewicz * values before the parent clock speed is set to new lower speed
35553f69967SBartlomiej Zolnierkiewicz * (this can result in too high speed of armclk output clocks).
35653f69967SBartlomiej Zolnierkiewicz */
35753f69967SBartlomiej Zolnierkiewicz if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
35853f69967SBartlomiej Zolnierkiewicz unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
359f707e891SSam Protsenko unsigned long alt_div, alt_div_mask = DIV_MASK;
36053f69967SBartlomiej Zolnierkiewicz
36153f69967SBartlomiej Zolnierkiewicz alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
36253f69967SBartlomiej Zolnierkiewicz WARN_ON(alt_div >= MAX_DIV);
36353f69967SBartlomiej Zolnierkiewicz
36478bc2312SSam Protsenko exynos_set_safe_div(cpuclk, alt_div, alt_div_mask);
36553f69967SBartlomiej Zolnierkiewicz div0 |= alt_div;
36653f69967SBartlomiej Zolnierkiewicz }
36753f69967SBartlomiej Zolnierkiewicz
36853f69967SBartlomiej Zolnierkiewicz /* select the alternate parent */
36978bc2312SSam Protsenko mux_reg = readl(base + regs->mux_sel);
37078bc2312SSam Protsenko writel(mux_reg | 1, base + regs->mux_sel);
371152cc747SSam Protsenko wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 2);
37253f69967SBartlomiej Zolnierkiewicz
37353f69967SBartlomiej Zolnierkiewicz /* alternate parent is active now. set the dividers */
37478bc2312SSam Protsenko writel(div0, base + regs->div_cpu0);
37578bc2312SSam Protsenko wait_until_divider_stable(base + regs->div_stat_cpu0, DIV_MASK_ALL);
37653f69967SBartlomiej Zolnierkiewicz
37778bc2312SSam Protsenko writel(div1, base + regs->div_cpu1);
37878bc2312SSam Protsenko wait_until_divider_stable(base + regs->div_stat_cpu1, DIV_MASK_ALL);
37953f69967SBartlomiej Zolnierkiewicz
38053f69967SBartlomiej Zolnierkiewicz spin_unlock_irqrestore(cpuclk->lock, flags);
38153f69967SBartlomiej Zolnierkiewicz return 0;
38253f69967SBartlomiej Zolnierkiewicz }
38353f69967SBartlomiej Zolnierkiewicz
38453f69967SBartlomiej Zolnierkiewicz /* handler for post-rate change notification from parent clock */
exynos5433_cpuclk_post_rate_change(struct clk_notifier_data * ndata,struct exynos_cpuclk * cpuclk)38553f69967SBartlomiej Zolnierkiewicz static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
386c9bc1f77SSam Protsenko struct exynos_cpuclk *cpuclk)
38753f69967SBartlomiej Zolnierkiewicz {
38878bc2312SSam Protsenko const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
389338f1c25SSam Protsenko void __iomem *base = cpuclk->base;
39053f69967SBartlomiej Zolnierkiewicz unsigned long div = 0, div_mask = DIV_MASK;
39153f69967SBartlomiej Zolnierkiewicz unsigned long mux_reg;
39253f69967SBartlomiej Zolnierkiewicz unsigned long flags;
39353f69967SBartlomiej Zolnierkiewicz
39453f69967SBartlomiej Zolnierkiewicz spin_lock_irqsave(cpuclk->lock, flags);
39553f69967SBartlomiej Zolnierkiewicz
39653f69967SBartlomiej Zolnierkiewicz /* select apll as the alternate parent */
39778bc2312SSam Protsenko mux_reg = readl(base + regs->mux_sel);
39878bc2312SSam Protsenko writel(mux_reg & ~1, base + regs->mux_sel);
399152cc747SSam Protsenko wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 1);
40053f69967SBartlomiej Zolnierkiewicz
40178bc2312SSam Protsenko exynos_set_safe_div(cpuclk, div, div_mask);
40253f69967SBartlomiej Zolnierkiewicz spin_unlock_irqrestore(cpuclk->lock, flags);
40353f69967SBartlomiej Zolnierkiewicz return 0;
40453f69967SBartlomiej Zolnierkiewicz }
40553f69967SBartlomiej Zolnierkiewicz
40661f4399cSSam Protsenko /* ---- Exynos850 ----------------------------------------------------------- */
40761f4399cSSam Protsenko
40861f4399cSSam Protsenko #define E850_DIV_RATIO_MASK GENMASK(3, 0)
40961f4399cSSam Protsenko #define E850_BUSY_MASK BIT(16)
41061f4399cSSam Protsenko
41161f4399cSSam Protsenko /* Max time for divider or mux to stabilize, usec */
41261f4399cSSam Protsenko #define E850_DIV_MUX_STAB_TIME 100
41361f4399cSSam Protsenko /* OSCCLK clock rate, Hz */
41461f4399cSSam Protsenko #define E850_OSCCLK (26 * MHZ)
41561f4399cSSam Protsenko
41661f4399cSSam Protsenko static const struct exynos_cpuclk_regs e850cl0_cpuclk_regs = {
41761f4399cSSam Protsenko .mux = 0x100c,
41861f4399cSSam Protsenko .divs = { 0x1800, 0x1808, 0x180c, 0x1810 },
41961f4399cSSam Protsenko };
42061f4399cSSam Protsenko
42161f4399cSSam Protsenko static const struct exynos_cpuclk_regs e850cl1_cpuclk_regs = {
42261f4399cSSam Protsenko .mux = 0x1000,
42361f4399cSSam Protsenko .divs = { 0x1800, 0x1808, 0x180c, 0x1810 },
42461f4399cSSam Protsenko };
42561f4399cSSam Protsenko
42661f4399cSSam Protsenko /*
42761f4399cSSam Protsenko * Set alternate parent rate to "rate" value or less.
42861f4399cSSam Protsenko *
42961f4399cSSam Protsenko * rate: Desired alt_parent rate, or 0 for max alt_parent rate
43061f4399cSSam Protsenko *
43161f4399cSSam Protsenko * Exynos850 doesn't have CPU clock divider in CMU_CPUCLx block (CMUREF divider
43261f4399cSSam Protsenko * doesn't affect CPU speed). So CPUCLx_SWITCH divider from CMU_TOP is used
43361f4399cSSam Protsenko * instead to adjust alternate parent speed.
43461f4399cSSam Protsenko *
43561f4399cSSam Protsenko * It's possible to use clk_set_max_rate() instead of this function, but it
43661f4399cSSam Protsenko * would set overly pessimistic rate values to alternate parent.
43761f4399cSSam Protsenko */
exynos850_alt_parent_set_max_rate(const struct clk_hw * alt_parent,unsigned long rate)43861f4399cSSam Protsenko static int exynos850_alt_parent_set_max_rate(const struct clk_hw *alt_parent,
43961f4399cSSam Protsenko unsigned long rate)
44061f4399cSSam Protsenko {
44161f4399cSSam Protsenko struct clk_hw *clk_div, *clk_divp;
44261f4399cSSam Protsenko unsigned long divp_rate, div_rate, div;
44361f4399cSSam Protsenko int ret;
44461f4399cSSam Protsenko
44561f4399cSSam Protsenko /* Divider from CMU_TOP */
44661f4399cSSam Protsenko clk_div = clk_hw_get_parent(alt_parent);
44761f4399cSSam Protsenko if (!clk_div)
44861f4399cSSam Protsenko return -ENOENT;
44961f4399cSSam Protsenko /* Divider's parent from CMU_TOP */
45061f4399cSSam Protsenko clk_divp = clk_hw_get_parent(clk_div);
45161f4399cSSam Protsenko if (!clk_divp)
45261f4399cSSam Protsenko return -ENOENT;
45361f4399cSSam Protsenko /* Divider input rate */
45461f4399cSSam Protsenko divp_rate = clk_hw_get_rate(clk_divp);
45561f4399cSSam Protsenko if (!divp_rate)
45661f4399cSSam Protsenko return -EINVAL;
45761f4399cSSam Protsenko
45861f4399cSSam Protsenko /* Calculate new alt_parent rate for integer divider value */
45961f4399cSSam Protsenko if (rate == 0)
46061f4399cSSam Protsenko div = 1;
46161f4399cSSam Protsenko else
46261f4399cSSam Protsenko div = DIV_ROUND_UP(divp_rate, rate);
46361f4399cSSam Protsenko div_rate = DIV_ROUND_UP(divp_rate, div);
46461f4399cSSam Protsenko WARN_ON(div >= MAX_DIV);
46561f4399cSSam Protsenko
46661f4399cSSam Protsenko /* alt_parent will propagate this change up to the divider */
46761f4399cSSam Protsenko ret = clk_set_rate(alt_parent->clk, div_rate);
46861f4399cSSam Protsenko if (ret)
46961f4399cSSam Protsenko return ret;
47061f4399cSSam Protsenko udelay(E850_DIV_MUX_STAB_TIME);
47161f4399cSSam Protsenko
47261f4399cSSam Protsenko return 0;
47361f4399cSSam Protsenko }
47461f4399cSSam Protsenko
47561f4399cSSam Protsenko /* Handler for pre-rate change notification from parent clock */
exynos850_cpuclk_pre_rate_change(struct clk_notifier_data * ndata,struct exynos_cpuclk * cpuclk)47661f4399cSSam Protsenko static int exynos850_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
47761f4399cSSam Protsenko struct exynos_cpuclk *cpuclk)
47861f4399cSSam Protsenko {
47961f4399cSSam Protsenko const unsigned int shifts[4] = { 16, 12, 8, 4 }; /* E850_CPU_DIV0() */
48061f4399cSSam Protsenko const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
48161f4399cSSam Protsenko const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
48261f4399cSSam Protsenko const struct clk_hw *alt_parent = cpuclk->alt_parent;
48361f4399cSSam Protsenko void __iomem *base = cpuclk->base;
48461f4399cSSam Protsenko unsigned long alt_prate = clk_hw_get_rate(alt_parent);
48561f4399cSSam Protsenko unsigned long flags;
48661f4399cSSam Protsenko u32 mux_reg;
48761f4399cSSam Protsenko size_t i;
48861f4399cSSam Protsenko int ret;
48961f4399cSSam Protsenko
49061f4399cSSam Protsenko /* No actions are needed when switching to or from OSCCLK parent */
49161f4399cSSam Protsenko if (ndata->new_rate == E850_OSCCLK || ndata->old_rate == E850_OSCCLK)
49261f4399cSSam Protsenko return 0;
49361f4399cSSam Protsenko
49461f4399cSSam Protsenko /* Find out the divider values to use for clock data */
49561f4399cSSam Protsenko while ((cfg_data->prate * 1000) != ndata->new_rate) {
49661f4399cSSam Protsenko if (cfg_data->prate == 0)
49761f4399cSSam Protsenko return -EINVAL;
49861f4399cSSam Protsenko cfg_data++;
49961f4399cSSam Protsenko }
50061f4399cSSam Protsenko
50161f4399cSSam Protsenko /*
50261f4399cSSam Protsenko * If the old parent clock speed is less than the clock speed of
50361f4399cSSam Protsenko * the alternate parent, then it should be ensured that at no point
50461f4399cSSam Protsenko * the armclk speed is more than the old_prate until the dividers are
50561f4399cSSam Protsenko * set. Also workaround the issue of the dividers being set to lower
50661f4399cSSam Protsenko * values before the parent clock speed is set to new lower speed
50761f4399cSSam Protsenko * (this can result in too high speed of armclk output clocks).
50861f4399cSSam Protsenko */
50961f4399cSSam Protsenko if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
51061f4399cSSam Protsenko unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
51161f4399cSSam Protsenko
51261f4399cSSam Protsenko ret = exynos850_alt_parent_set_max_rate(alt_parent, tmp_rate);
51361f4399cSSam Protsenko if (ret)
51461f4399cSSam Protsenko return ret;
51561f4399cSSam Protsenko }
51661f4399cSSam Protsenko
51761f4399cSSam Protsenko spin_lock_irqsave(cpuclk->lock, flags);
51861f4399cSSam Protsenko
51961f4399cSSam Protsenko /* Select the alternate parent */
52061f4399cSSam Protsenko mux_reg = readl(base + regs->mux);
52161f4399cSSam Protsenko writel(mux_reg | 1, base + regs->mux);
52261f4399cSSam Protsenko wait_until_mux_stable(base + regs->mux, 16, 1, 0);
52361f4399cSSam Protsenko
52461f4399cSSam Protsenko /* Alternate parent is active now. Set the dividers */
52561f4399cSSam Protsenko for (i = 0; i < ARRAY_SIZE(shifts); ++i) {
52661f4399cSSam Protsenko unsigned long div = (cfg_data->div0 >> shifts[i]) & 0xf;
52761f4399cSSam Protsenko u32 val;
52861f4399cSSam Protsenko
52961f4399cSSam Protsenko val = readl(base + regs->divs[i]);
53061f4399cSSam Protsenko val = (val & ~E850_DIV_RATIO_MASK) | div;
53161f4399cSSam Protsenko writel(val, base + regs->divs[i]);
53261f4399cSSam Protsenko wait_until_divider_stable(base + regs->divs[i], E850_BUSY_MASK);
53361f4399cSSam Protsenko }
53461f4399cSSam Protsenko
53561f4399cSSam Protsenko spin_unlock_irqrestore(cpuclk->lock, flags);
53661f4399cSSam Protsenko
53761f4399cSSam Protsenko return 0;
53861f4399cSSam Protsenko }
53961f4399cSSam Protsenko
54061f4399cSSam Protsenko /* Handler for post-rate change notification from parent clock */
exynos850_cpuclk_post_rate_change(struct clk_notifier_data * ndata,struct exynos_cpuclk * cpuclk)54161f4399cSSam Protsenko static int exynos850_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
54261f4399cSSam Protsenko struct exynos_cpuclk *cpuclk)
54361f4399cSSam Protsenko {
54461f4399cSSam Protsenko const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
54561f4399cSSam Protsenko const struct clk_hw *alt_parent = cpuclk->alt_parent;
54661f4399cSSam Protsenko void __iomem *base = cpuclk->base;
54761f4399cSSam Protsenko unsigned long flags;
54861f4399cSSam Protsenko u32 mux_reg;
54961f4399cSSam Protsenko
55061f4399cSSam Protsenko /* No actions are needed when switching to or from OSCCLK parent */
55161f4399cSSam Protsenko if (ndata->new_rate == E850_OSCCLK || ndata->old_rate == E850_OSCCLK)
55261f4399cSSam Protsenko return 0;
55361f4399cSSam Protsenko
55461f4399cSSam Protsenko spin_lock_irqsave(cpuclk->lock, flags);
55561f4399cSSam Protsenko
55661f4399cSSam Protsenko /* Select main parent (PLL) for mux */
55761f4399cSSam Protsenko mux_reg = readl(base + regs->mux);
55861f4399cSSam Protsenko writel(mux_reg & ~1, base + regs->mux);
55961f4399cSSam Protsenko wait_until_mux_stable(base + regs->mux, 16, 1, 0);
56061f4399cSSam Protsenko
56161f4399cSSam Protsenko spin_unlock_irqrestore(cpuclk->lock, flags);
56261f4399cSSam Protsenko
56361f4399cSSam Protsenko /* Set alt_parent rate back to max */
56461f4399cSSam Protsenko return exynos850_alt_parent_set_max_rate(alt_parent, 0);
56561f4399cSSam Protsenko }
56661f4399cSSam Protsenko
567be20ccc1SSam Protsenko /* -------------------------------------------------------------------------- */
568be20ccc1SSam Protsenko
569be20ccc1SSam Protsenko /* Common round rate callback usable for all types of CPU clocks */
exynos_cpuclk_round_rate(struct clk_hw * hw,unsigned long drate,unsigned long * prate)570be20ccc1SSam Protsenko static long exynos_cpuclk_round_rate(struct clk_hw *hw, unsigned long drate,
571be20ccc1SSam Protsenko unsigned long *prate)
572be20ccc1SSam Protsenko {
573be20ccc1SSam Protsenko struct clk_hw *parent = clk_hw_get_parent(hw);
574be20ccc1SSam Protsenko *prate = clk_hw_round_rate(parent, drate);
575be20ccc1SSam Protsenko return *prate;
576be20ccc1SSam Protsenko }
577be20ccc1SSam Protsenko
578be20ccc1SSam Protsenko /* Common recalc rate callback usable for all types of CPU clocks */
exynos_cpuclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)579be20ccc1SSam Protsenko static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw,
580be20ccc1SSam Protsenko unsigned long parent_rate)
581be20ccc1SSam Protsenko {
582be20ccc1SSam Protsenko /*
583be20ccc1SSam Protsenko * The CPU clock output (armclk) rate is the same as its parent
584be20ccc1SSam Protsenko * rate. Although there exist certain dividers inside the CPU
585be20ccc1SSam Protsenko * clock block that could be used to divide the parent clock,
586be20ccc1SSam Protsenko * the driver does not make use of them currently, except during
587be20ccc1SSam Protsenko * frequency transitions.
588be20ccc1SSam Protsenko */
589be20ccc1SSam Protsenko return parent_rate;
590be20ccc1SSam Protsenko }
591be20ccc1SSam Protsenko
592be20ccc1SSam Protsenko static const struct clk_ops exynos_cpuclk_clk_ops = {
593be20ccc1SSam Protsenko .recalc_rate = exynos_cpuclk_recalc_rate,
594be20ccc1SSam Protsenko .round_rate = exynos_cpuclk_round_rate,
595be20ccc1SSam Protsenko };
596be20ccc1SSam Protsenko
59753f69967SBartlomiej Zolnierkiewicz /*
598ddeac8d9SThomas Abraham * This notifier function is called for the pre-rate and post-rate change
599ddeac8d9SThomas Abraham * notifications of the parent clock of cpuclk.
600ddeac8d9SThomas Abraham */
exynos_cpuclk_notifier_cb(struct notifier_block * nb,unsigned long event,void * data)601ddeac8d9SThomas Abraham static int exynos_cpuclk_notifier_cb(struct notifier_block *nb,
602ddeac8d9SThomas Abraham unsigned long event, void *data)
603ddeac8d9SThomas Abraham {
604ddeac8d9SThomas Abraham struct clk_notifier_data *ndata = data;
605ddeac8d9SThomas Abraham struct exynos_cpuclk *cpuclk;
606ddeac8d9SThomas Abraham int err = 0;
607ddeac8d9SThomas Abraham
608ddeac8d9SThomas Abraham cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
609ddeac8d9SThomas Abraham
610ddeac8d9SThomas Abraham if (event == PRE_RATE_CHANGE)
6119c746e5aSSam Protsenko err = cpuclk->chip->pre_rate_cb(ndata, cpuclk);
612ddeac8d9SThomas Abraham else if (event == POST_RATE_CHANGE)
6139c746e5aSSam Protsenko err = cpuclk->chip->post_rate_cb(ndata, cpuclk);
61453f69967SBartlomiej Zolnierkiewicz
61553f69967SBartlomiej Zolnierkiewicz return notifier_from_errno(err);
61653f69967SBartlomiej Zolnierkiewicz }
61753f69967SBartlomiej Zolnierkiewicz
6189c746e5aSSam Protsenko static const struct exynos_cpuclk_chip exynos_clkcpu_chips[] = {
6199c746e5aSSam Protsenko [CPUCLK_LAYOUT_E4210] = {
62078bc2312SSam Protsenko .regs = &e4210_cpuclk_regs,
6219c746e5aSSam Protsenko .pre_rate_cb = exynos_cpuclk_pre_rate_change,
6229c746e5aSSam Protsenko .post_rate_cb = exynos_cpuclk_post_rate_change,
6239c746e5aSSam Protsenko },
6249c746e5aSSam Protsenko [CPUCLK_LAYOUT_E5433] = {
62578bc2312SSam Protsenko .regs = &e5433_cpuclk_regs,
6269c746e5aSSam Protsenko .pre_rate_cb = exynos5433_cpuclk_pre_rate_change,
6279c746e5aSSam Protsenko .post_rate_cb = exynos5433_cpuclk_post_rate_change,
6289c746e5aSSam Protsenko },
62961f4399cSSam Protsenko [CPUCLK_LAYOUT_E850_CL0] = {
63061f4399cSSam Protsenko .regs = &e850cl0_cpuclk_regs,
63161f4399cSSam Protsenko .pre_rate_cb = exynos850_cpuclk_pre_rate_change,
63261f4399cSSam Protsenko .post_rate_cb = exynos850_cpuclk_post_rate_change,
63361f4399cSSam Protsenko },
63461f4399cSSam Protsenko [CPUCLK_LAYOUT_E850_CL1] = {
63561f4399cSSam Protsenko .regs = &e850cl1_cpuclk_regs,
63661f4399cSSam Protsenko .pre_rate_cb = exynos850_cpuclk_pre_rate_change,
63761f4399cSSam Protsenko .post_rate_cb = exynos850_cpuclk_post_rate_change,
63861f4399cSSam Protsenko },
6399c746e5aSSam Protsenko };
6409c746e5aSSam Protsenko
641ddeac8d9SThomas Abraham /* helper function to register a CPU clock */
exynos_register_cpu_clock(struct samsung_clk_provider * ctx,const struct samsung_cpu_clock * clk_data)642ac48ea3bSWill McVicker static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
64384d42803SSam Protsenko const struct samsung_cpu_clock *clk_data)
644ddeac8d9SThomas Abraham {
64584d42803SSam Protsenko const struct clk_hw *parent, *alt_parent;
64684d42803SSam Protsenko struct clk_hw **hws;
647ddeac8d9SThomas Abraham struct exynos_cpuclk *cpuclk;
648ddeac8d9SThomas Abraham struct clk_init_data init;
649ff8e0ff9SSylwester Nawrocki const char *parent_name;
65084d42803SSam Protsenko unsigned int num_cfgs;
651ddeac8d9SThomas Abraham int ret = 0;
652ddeac8d9SThomas Abraham
65384d42803SSam Protsenko hws = ctx->clk_data.hws;
65484d42803SSam Protsenko parent = hws[clk_data->parent_id];
65584d42803SSam Protsenko alt_parent = hws[clk_data->alt_parent_id];
656ff8e0ff9SSylwester Nawrocki if (IS_ERR(parent) || IS_ERR(alt_parent)) {
657ff8e0ff9SSylwester Nawrocki pr_err("%s: invalid parent clock(s)\n", __func__);
658ff8e0ff9SSylwester Nawrocki return -EINVAL;
659ff8e0ff9SSylwester Nawrocki }
660ff8e0ff9SSylwester Nawrocki
661ddeac8d9SThomas Abraham cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
662ddeac8d9SThomas Abraham if (!cpuclk)
663ddeac8d9SThomas Abraham return -ENOMEM;
664ddeac8d9SThomas Abraham
665ff8e0ff9SSylwester Nawrocki parent_name = clk_hw_get_name(parent);
666ff8e0ff9SSylwester Nawrocki
66784d42803SSam Protsenko init.name = clk_data->name;
668ddeac8d9SThomas Abraham init.flags = CLK_SET_RATE_PARENT;
669ff8e0ff9SSylwester Nawrocki init.parent_names = &parent_name;
670ddeac8d9SThomas Abraham init.num_parents = 1;
671ddeac8d9SThomas Abraham init.ops = &exynos_cpuclk_clk_ops;
672ddeac8d9SThomas Abraham
673ff8e0ff9SSylwester Nawrocki cpuclk->alt_parent = alt_parent;
674ddeac8d9SThomas Abraham cpuclk->hw.init = &init;
675338f1c25SSam Protsenko cpuclk->base = ctx->reg_base + clk_data->offset;
676ddeac8d9SThomas Abraham cpuclk->lock = &ctx->lock;
67784d42803SSam Protsenko cpuclk->flags = clk_data->flags;
678ddeac8d9SThomas Abraham cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
6799c746e5aSSam Protsenko cpuclk->chip = &exynos_clkcpu_chips[clk_data->reg_layout];
680ddeac8d9SThomas Abraham
681ff8e0ff9SSylwester Nawrocki ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);
682ddeac8d9SThomas Abraham if (ret) {
683ddeac8d9SThomas Abraham pr_err("%s: failed to register clock notifier for %s\n",
68484d42803SSam Protsenko __func__, clk_data->name);
685ddeac8d9SThomas Abraham goto free_cpuclk;
686ddeac8d9SThomas Abraham }
687ddeac8d9SThomas Abraham
68884d42803SSam Protsenko /* Find count of configuration rates in cfg */
68984d42803SSam Protsenko for (num_cfgs = 0; clk_data->cfg[num_cfgs].prate != 0; )
69084d42803SSam Protsenko num_cfgs++;
69184d42803SSam Protsenko
692*76667188SAndy Shevchenko cpuclk->cfg = kmemdup_array(clk_data->cfg, num_cfgs, sizeof(*cpuclk->cfg),
69384d42803SSam Protsenko GFP_KERNEL);
694ddeac8d9SThomas Abraham if (!cpuclk->cfg) {
695ddeac8d9SThomas Abraham ret = -ENOMEM;
696ddeac8d9SThomas Abraham goto unregister_clk_nb;
697ddeac8d9SThomas Abraham }
698ddeac8d9SThomas Abraham
699ecb1f1f7SMarek Szyprowski ret = clk_hw_register(NULL, &cpuclk->hw);
700ecb1f1f7SMarek Szyprowski if (ret) {
70184d42803SSam Protsenko pr_err("%s: could not register cpuclk %s\n", __func__,
70284d42803SSam Protsenko clk_data->name);
703ddeac8d9SThomas Abraham goto free_cpuclk_data;
704ddeac8d9SThomas Abraham }
705ddeac8d9SThomas Abraham
70684d42803SSam Protsenko samsung_clk_add_lookup(ctx, &cpuclk->hw, clk_data->id);
707ddeac8d9SThomas Abraham return 0;
708ddeac8d9SThomas Abraham
709ddeac8d9SThomas Abraham free_cpuclk_data:
710ddeac8d9SThomas Abraham kfree(cpuclk->cfg);
711ddeac8d9SThomas Abraham unregister_clk_nb:
712ff8e0ff9SSylwester Nawrocki clk_notifier_unregister(parent->clk, &cpuclk->clk_nb);
713ddeac8d9SThomas Abraham free_cpuclk:
714ddeac8d9SThomas Abraham kfree(cpuclk);
715ddeac8d9SThomas Abraham return ret;
716ddeac8d9SThomas Abraham }
7173270ffe8SWill McVicker
samsung_clk_register_cpu(struct samsung_clk_provider * ctx,const struct samsung_cpu_clock * list,unsigned int nr_clk)7183270ffe8SWill McVicker void __init samsung_clk_register_cpu(struct samsung_clk_provider *ctx,
7193270ffe8SWill McVicker const struct samsung_cpu_clock *list, unsigned int nr_clk)
7203270ffe8SWill McVicker {
7213270ffe8SWill McVicker unsigned int idx;
7223270ffe8SWill McVicker
72384d42803SSam Protsenko for (idx = 0; idx < nr_clk; idx++)
72484d42803SSam Protsenko exynos_register_cpu_clock(ctx, &list[idx]);
7253270ffe8SWill McVicker }
726