tegra234-clock.h - OpenGrok cross reference for /linux/include/dt-bindings/clock/tegra234-clock.h

Lines Matching +full:divider +full:- +full:clock
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
9  * @defgroup bpmp_clock_ids Clock ID's
36 /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
52  * divided by the divider controlled by ACLK_CLK_DIVISOR in
56 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */
58 /** @brief clock recovered from EAVB input */
60 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */
62 /** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */
64 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */
73  * @brief controls the EMC clock frequency.
74  * @details Doing a clk_set_rate on this clock will select the
75  * appropriate clock source, program the source rate and execute a
76  * specific sequence to switch to the new clock source for both memory
81 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */
83 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */
87 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider gated output */
126 /** @brief clock recovered from I2S1 input */
130 /** @brief clock recovered from I2S2 input */
134 /** @brief clock recovered from I2S3 input */
138 /** @brief clock recovered from I2S4 input */
142 /** @brief clock recovered from I2S5 input */
146 /** @brief clock recovered from I2S6 input */
150 /** @brief Monitored branch of EQOS_RX clock */
152 /** @brief CLK_RST_CONTROLLER_MAUDCLK_OUT_SWITCH_DIVIDER switch divider output (maudclk) */
156 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
170 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
178 /** @brief CLK_RST_CONTROLLER_HUBCLK_OUT_SWITCH_DIVIDER switch divider output (hubclk) */
180 /** @brief CLK_RST_CONTROLLER_DISPCLK_SWITCH_DIVIDER switch divider output (dispclk) */
182 /** @brief RG_CLK_CTRL__0_DIV divider output (nvdisplay_p0_clk) */
184 /** @brief RG_CLK_CTRL__1_DIV divider output (nvdisplay_p1_clk) */
194 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH switch divider output */
208 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
228 /** @brief CLK_RST_CONTROLLER_RCE_NIC_RATE divider output */
230 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW switch divider output */
234 /** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
242 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider gated output */
250 /** @brief SOR_PLL_REF_CLK_CTRL__0_DIV divider output */
254 /** @brief SOR_PLL_REF_CLK_CTRL__1_DIV divider output */
258 /** @brief SOR_CLK_CTRL__0_DIV divider output */
328 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_CSITE switch divider output */
330 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_IST switch divider output */
352 /** @brief DP macro feedback clock (same as LINKA_SYM CLKOUT) */
364 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTI switch divider output (uarti_r_clk) */
366 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ switch divider output (uartj_r_clk) */
368 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTH switch divider output */
372 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output (qspi0_2x_pm_clk) */
374 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output (qspi1_2x_pm_clk) */
376 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 (qspi0_pm…
378 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 (qspi1_pm…
380 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST switch divider output */
382 /** @brief NAFLL clock source for BPMP */
384 /** @brief NAFLL clock source for SCE */
386 /** @brief NAFLL clock source for NVDEC */
388 /** @brief NAFLL clock source for NVJPG */
390 /** @brief NAFLL clock source for TSEC */
392 /** @brief NAFLL clock source for VI */
394 /** @brief NAFLL clock source for SE */
396 /** @brief NAFLL clock source for NVENC */
398 /** @brief NAFLL clock source for ISP */
400 /** @brief NAFLL clock source for VIC */
402 /** @brief NAFLL clock source for AXICBB */
404 /** @brief NAFLL clock source for NVJPG1 */
406 /** @brief NAFLL clock source for PVA core */
408 /** @brief NAFLL clock source for PVA VPS */
410 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0 switch divider output (dbgapb_clk) */
412 /** @brief NAFLL clock source for RCE */
414 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_LA switch divider output (la_r_clk) */
416 /** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTD */
420 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
434 /** @brief Monitored branch of PEX0_C0_CORE clock */
436 /** @brief Monitored branch of PEX0_C1_CORE clock */
438 /** @brief Monitored branch of PEX0_C2_CORE clock */
440 /** @brief Monitored branch of PEX0_C3_CORE clock */
442 /** @brief Monitored branch of PEX0_C4_CORE clock */
444 /** @brief Monitored branch of PEX1_C5_CORE clock */
446 /** @brief Monitored branch of PEX1_C6_CORE clock */
462 /** @brief Monitored branch of PEX2_C7_CORE clock */
464 /** @brief Monitored branch of PEX2_C8_CORE clock */
466 /** @brief Monitored branch of PEX2_C9_CORE clock */
468 /** @brief Monitored branch of PEX2_C10_CORE clock */
470 /** @brief RX clock recovered from MGBE0 lane input */
472 /** @brief RX clock recovered from MGBE1 lane input */
474 /** @brief RX clock recovered from MGBE2 lane input */
476 /** @brief RX clock recovered from MGBE3 lane input */
478 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP switch divider output */
480 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT switch divider output */
482 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT switch divider output */
484 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT switch divider output */
486 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT switch divider output */
488 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP switch divider output */
490 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT switch divider output */
494 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST switch divider output  */
500 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON switch divider output */
506 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS switch divider output */
512 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS switch divider output */
518 /** @brief NAFLL clock source for CPU cluster 0 */
521 /** @brief NAFLL clock source for CPU cluster 1 */
524 /** @brief NAFLL clock source for CPU cluster 2 */
527 /** @brief CLK_RST_CONTROLLER_CAN1_CORE_RATE divider output */
529 /** @brief CLK_RST_CONTROLLER_CAN2_CORE_RATE divider outputt */
531 /** @brief CLK_RST_CONTROLLER_PLLA1_OUT1 switch divider output */
537 /** @brief 32K input clock provided by PMIC */
539 /** @brief Fixed 48MHz clock divided down from utmipll */
541 /** @brief Fixed 480MHz clock divided down from utmipll */
545 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI switch divider output */
547 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS switch divider output */
559 /** @brief GPU system clock */
563 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider free running clk */
565 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC switch divider output */
569 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSC switch divider output */
583 /** @brief CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER skip divider output */
585 /** @brief Dummy clock to ensure minimum SoC voltage for fuse burning */
591 /** @brief output of EMC CDB side A fixed (DIV4)  divider */
593 /** @brief output of EMC CDB side B fixed (DIV4)  divider */
595 /** @brief output of EMC CDB side C fixed (DIV4)  divider */
597 /** @brief output of EMC CDB side D fixed (DIV4)  divider */
605 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM switch divider output */
607 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSENSE switch divider output */
609 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider free running clk */
611 /** @brief NAFLL clock source for OFA */
613 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_OFA switch divider output */
615 /** @brief NAFLL clock source for SEU1 */
617 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider gated output */
625 /** @brief output of divider CLK_RST_CONTROLLER_DCE_NIC_RATE */
627 /** @brief NAFLL clock source for DCE */
629 /** @brief Monitored branch of MPHY_L0_RX_ANA clock */
631 /** @brief Monitored branch of MPHY_L1_RX_ANA clock */
633 /** @brief ungated version of TX symbol clock after fixed 1/2 divider */
635 /** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
639 /** @brief output of SW_MPHY_L0_TX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */
641 /** @brief output of SW_MPHY_L0_TX_LS_3XBIT divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */
643 /** @brief LS/HS divider mux SW_MPHY_L0_TX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */
645 /** @brief Monitored branch of MPHY_L0_TX_SYMB clock */
647 /** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
649 /** @brief output of SW_MPHY_L0_RX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */
651 /** @brief output of SW_MPHY_L0_RX_LS_BIT divider in  CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */
653 /** @brief LS/HS divider mux SW_MPHY_L0_RX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */
655 /** @brief Monitored branch of MPHY_L0_RX_SYMB clock */
657 /** @brief Monitored branch of MBGE0 RX input clock */
659 /** @brief Monitored branch of MBGE1 RX input clock */
661 /** @brief Monitored branch of MBGE2 RX input clock */
663 /** @brief Monitored branch of MBGE3 RX input clock */
675 /** @brief GBE_UPHY_MGBES_APP_CLK switch divider gated output */
681 /** @brief RX PCS clock recovered from MGBE0 lane input */
683 /** @brief RX PCS clock recovered from MGBE1 lane input */
685 /** @brief RX PCS clock recovered from MGBE2 lane input */
687 /** @brief RX PCS clock recovered from MGBE3 lane input */
691 /** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */
693 /** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */
695 /** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */
705 /** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */
709 /** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */
711 /** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */
713 /** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */
723 /** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */
727 /** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */
729 /** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */
731 /** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */
741 /** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */
745 /** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */
747 /** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */
749 /** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */
759 /** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */
761 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_RX_BYP switch divider output */
763 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL0_MGMT switch divider output */
765 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL1_MGMT switch divider output */
767 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL2_MGMT switch divider output */
773 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider ungated output */
775 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL1_MGMT switch divider output */
779 /** @brief clock recovered from I2S7 input */
787 /** @brief clock recovered from I2S8 input */
795 /** @brief NAFLL clock source for GPU GPC0 */
797 /** @brief NAFLL clock source for GPU GPC1 */
799 /** @brief NAFLL clock source for GPU SYSCLK */
801 /** @brief NAFLL clock source for CPU cluster 0 DSUCLK */
804 /** @brief NAFLL clock source for CPU cluster 1 DSUCLK */
807 /** @brief NAFLL clock source for CPU cluster 2 DSUCLK */
842 /** @brief VPLL0 reference clock */
858 /** @brief CLK_RST_CONTROLLER_DSI_LP_SWITCH_DIVIDER switch divider output (dsi_lp_clk) */
860 /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
874 /** @brief Link clock input from DP macro brick PLL */
876 /** @brief SOR AFIFO clock outut */
890 /** @brief output of fixed (DIV2) MC HUB divider */
892 /** @brief output of divider controlled by EMC side A MC_EMC_SAFE_SAME_FREQ */
894 /** @brief output of divider controlled by EMC side B MC_EMC_SAFE_SAME_FREQ */
896 /** @brief output of divider controlled by EMC side C MC_EMC_SAFE_SAME_FREQ */
898 /** @brief output of divider controlled by EMC side D MC_EMC_SAFE_SAME_FREQ */